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@kroening kroening commented Nov 13, 2025

This adds support for SystemVerilog type parameter ports (1800-2017 6.20.3).

@kroening kroening force-pushed the type_parameter_ports1 branch 10 times, most recently from 437b8c6 to e1da548 Compare November 21, 2025 18:16
@kroening kroening force-pushed the type_parameter_ports1 branch 2 times, most recently from 3478763 to 3c227f1 Compare December 1, 2025 07:45
@kroening kroening force-pushed the type_parameter_ports1 branch 5 times, most recently from 38b04f0 to b25cb76 Compare December 7, 2025 00:46
This replaces the remaining uses of symbol_exprt for simple identifiers in
the Verilog parse tree by verilog_identifier_exprt.
Verilog typedefs need to be resolved by the type checker, to account for
parameter-dependent prefixes.
This adds support for SystemVerilog type parameter ports (1800-2017 6.20.3).
@kroening kroening force-pushed the type_parameter_ports1 branch from b25cb76 to 0dac84f Compare December 7, 2025 17:49
@kroening kroening marked this pull request as ready for review December 7, 2025 17:51
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