SystemVerilog: type parameter ports

This adds support for SystemVerilog type parameter ports (1800-2017 6.20.3).

Author: kroening

CHANGELOG

@@ -2,6 +2,7 @@
 
 * Verilog: fix for typed parameter ports
 * SystemVerilog: fix for type parameters
+* SystemVerilog: type parameter ports
 * SMV: word constants
 * SMV: IVAR declarations
 * SMV: bit selection operator

regression/verilog/modules/parameter_ports4.desc

@@ -0,0 +1,7 @@
+CORE
+type_parameter_port1.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+--

regression/verilog/modules/type_parameter_port1.desc

@@ -0,0 +1,7 @@
+CORE
+type_parameter_port2.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+--

regression/verilog/modules/parameter_ports4.sv renamed to regression/verilog/modules/type_parameter_port1.sv

@@ -0,0 +1,13 @@
+module sub #(parameter type T = int)();
+
+  var T my_var;
+
+endmodule
+
+module main;
+
+  sub #(.T(byte)) submodule();
+
+  p1: assert final ($bits(submodule.my_var) == 8);
+
+endmodule // main

regression/verilog/modules/type_parameter_port2.desc

@@ -0,0 +1,7 @@
+CORE
+type_parameter_port3.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+--

regression/verilog/modules/type_parameter_port2.sv

@@ -0,0 +1,13 @@
+module sub #(type T = int)();
+
+  var T my_var;
+
+endmodule
+
+module main;
+
+  sub #(byte) submodule();
+
+  p1: assert final ($bits(submodule.my_var) == 8);
+
+endmodule // main

regression/verilog/modules/type_parameter_port3.desc

@@ -0,0 +1,7 @@
+CORE
+type_parameter_port4.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+--

regression/verilog/modules/type_parameter_port3.sv

@@ -0,0 +1,13 @@
+module sub #(parameter N = 32, localparam type T = bit[N-1:0])();
+
+  var T my_var;
+
+endmodule
+
+module main;
+
+  sub #(8) submodule();
+
+  p1: assert final ($bits(submodule.my_var) == 8);
+
+endmodule // main