Skip to content

Pull requests: diffblue/hw-cbmc

New pull request New
53 Open 1,350 Closed
53 Open 1,350 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Reviews
Filter by reviews
No reviews Review required Approved review Changes requested
Assignee
Filter by who’s assigned
Assigned to nobody Loading
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Pull requests list

Verilog: use resolver for typedefs Verilog
#1466 opened Dec 7, 2025 by kroening Loading…
Verilog: create symbol_exprt without ID_base_name field Verilog
#1465 opened Dec 6, 2025 by kroening Loading…
Remove ebmc_baset cleanup
#1464 opened Dec 6, 2025 by kroening Loading…
move --show-ldg and --compute-ct out of ebmc_baset cleanup
#1463 opened Dec 6, 2025 by kroening Loading…
Verilog: use verilog_identifier_exprt for port names cleanup Verilog
#1462 opened Dec 6, 2025 by kroening Loading…
generate stable AIGs engines
#1460 opened Dec 5, 2025 by kroening Loading…
Use verilog_identifier_exprt cleanup Verilog
#1459 opened Dec 5, 2025 by kroening • Draft
ebmc language interface implementation for Verilog Verilog
#1454 opened Dec 2, 2025 by kroening • Draft
SystemVerilog: sequence and property ports Verilog
#1436 opened Nov 24, 2025 by kroening • Draft
Make the counter synthesizable, update comment
#1414 opened Nov 15, 2025 by ShashankVM • Draft
1
SystemVerilog: type parameter ports Verilog
#1412 opened Nov 13, 2025 by kroening • Draft
SMV: pre-traversal identifier conversion SMV
#1409 opened Nov 12, 2025 by kroening • Draft
SMV output: use IVAR
#1396 opened Nov 9, 2025 by kroening • Draft
SMV: use NuSMV's operator precedence SMV
#1382 opened Nov 2, 2025 by kroening • Draft
netlist conversion: replace recursion by explicit stack engines
#1373 opened Oct 29, 2025 by kroening • Draft
bump CBMC dependency to release 6.8.0 dependencies Pull requests that update a dependency file
#1364 opened Oct 26, 2025 by kroening • Draft
SMV: enums are global SMV
#1358 opened Oct 23, 2025 by kroening Loading…
Verilog: fix semantics of cover disable iff Verilog
#1346 opened Oct 20, 2025 by kroening • Draft
Generate VCD file for each cover statement
#1296 opened Oct 3, 2025 by ShashankVM Loading…
1
10
SystemVerilog .* wildcard port connections Verilog
#1240 opened Aug 26, 2025 by kroening • Draft
SMV: union operator SMV
#1186 opened Jul 7, 2025 by kroening • Draft
split up ltl_sva_to_stringt::rec cleanup engines
#1171 opened Jun 27, 2025 by kroening • Draft
SVA: strengthen typing of sva_sequence_concatenation_exprt cleanup
#1161 opened Jun 17, 2025 by kroening • Draft
1
NeurIPS 2025 SystemVerilog benchmarks
#1147 opened Jun 6, 2025 by kroening Loading…
SMV: bit selection operator SMV
#1113 opened May 18, 2025 by kroening • Draft
ProTip! Updated in the last three days: updated:>2025-12-03.