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maksyukimaksyuki
committed
Merge branch 'tc-l2' into dev
2 parents 5850590 + 1bc6f1f commit b84d804

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12 files changed

+164
-109
lines changed

12 files changed

+164
-109
lines changed

‎.gitignore‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,4 +12,5 @@ DRAMsim3
1212
dramsim3.json
1313
dramsim3.txt
1414
dramsim3epoch.json
15-
*.vcd
15+
*.vcd
16+
*.wave

‎rtl/Makefile‎

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -40,11 +40,13 @@ SOC_VSRC_INCLPATH += -I$(ROOT_PATH)/ysyxSoC/ysyx/peripheral/spi/rtl
4040
SOC_CSRC_INCLPATH += -I$(SOC_CSRC_HOME)
4141
SOC_CSRC_INCLPATH += -I$(SOC_CSRC_LIB_HOME)
4242

43-
SOC_CXXFLAGS += -std=c++11 -static -Wall $(SOC_CSRC_INCLPATH)
43+
# if want to ouput vcd wave, replace '-DDUMP_WAVE_FST' to '-DDUMP_WAVE_VCD',
44+
# replace '--trace-fst' to '--trace'
45+
SOC_CXXFLAGS += -std=c++11 -static -Wall $(SOC_CSRC_INCLPATH) -DDUMP_WAVE_FST
4446
SOC_FLAGS += --cc --exe --top-module $(SOC_VSRC_TOP)
4547
SOC_FLAGS += --x-assign unique -O3 -CFLAGS "$(SOC_CXXFLAGS)"
46-
SOC_FLAGS += --trace --assert --stats-vars --output-split 30000 --output-split-cfuncs 30000
47-
SOC_FLAGS += --timescale "1ns/1ns" -Wno-fatal --trace
48+
SOC_FLAGS += --trace-fst --assert --stats-vars --output-split 30000 --output-split-cfuncs 30000
49+
SOC_FLAGS += --timescale "1ns/1ns" -Wno-fatal
4850
SOC_FLAGS += -o $(BUILD_DIR)/soc/emu
4951
SOC_FLAGS += -Mdir $(BUILD_DIR)/soc/emu-compile
5052
SOC_FLAGS += $(SOC_VSRC_INCLPATH) $(SOC_CXXFILES) $(SOC_VXXFILES)
@@ -239,14 +241,14 @@ socLintCheck: socNameCheck
239241
$(MAKE) -C $(YSYXSOC_HOME)/lint/ lint-unused
240242
@echo -e "\033[1;32mlint-unused check done\033[0m"
241243

242-
socPrevBuild:
244+
socPrevBuild: diffAllBuild socTopModify
243245
# FIXME: if only need to moidfy core, commit it
244246
# @cp $(YSYXSOC_HOME)/soc/ysyxSoCFull.v $(BUILD_DIR)/soc
245247
@sed -i s/ysyx_000000/ysyx_210324/g $(BUILD_DIR)/soc/ysyxSoCFull.v
246248
verilator $(SOC_FLAGS)
247249

248250
socBuild: socPrevBuild
249-
$(MAKE) VM_PARALLEL_BUILDS=1 OPT_FAST="-O3" -C $(SOC_COMPILE_HOME) -f V$(SOC_VSRC_TOP).mk
251+
$(MAKE) VM_PARALLEL_BUILDS=1 OPT_FAST="-O3" -C $(SOC_COMPILE_HOME) -f V$(SOC_VSRC_TOP).mk -j2
250252

251253
socSimRun:
252254
$(SOC_VSRC_HOME)/emu -i $(YSYXSOC_HOME)/program/bin/flash/hello-flash.bin --dump-wave

‎rtl/tc_l2/src/main/csrc/emu.h‎

Lines changed: 56 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,11 @@
11
#include <unistd.h>
22
#include <getopt.h>
33

4+
#ifdef DUMP_WAVE_VCD
45
#include <verilated_vcd_c.h>
6+
#elif DUMP_WAVE_FST
7+
#include <verilated_fst_c.h>
8+
#endif
59
#include <verilated.h>
610
#include <VysyxSoCFull.h>
711

@@ -26,47 +30,53 @@ class Emulator
2630
flash_init(args.image);
2731

2832
printf("Initializing and resetting DUT ...\n");
29-
dut_ptr = new VysyxSoCFull;
30-
dut_ptr->reset = 1;
33+
dutPtr = new VysyxSoCFull;
34+
dutPtr->reset = 1;
3135
for (int i = 0; i < 10; i++)
3236
{
33-
dut_ptr->clock = 0;
34-
dut_ptr->eval();
35-
dut_ptr->clock = 1;
36-
dut_ptr->eval();
37+
dutPtr->clock = 0;
38+
dutPtr->eval();
39+
dutPtr->clock = 1;
40+
dutPtr->eval();
3741
}
38-
dut_ptr->clock = 0;
39-
dut_ptr->reset = 0;
40-
dut_ptr->eval();
42+
dutPtr->clock = 0;
43+
dutPtr->reset = 0;
44+
dutPtr->eval();
4145

42-
if (args.dump_wave)
46+
if (args.dumpWave)
4347
{
48+
#ifdef DUMP_WAVE_VCD
49+
wavePtr = new VerilatedVcdC;
50+
#elif DUMP_WAVE_FST
51+
wavePtr = new VerilatedFstC;
52+
#endif
4453
Verilated::traceEverOn(true);
45-
printf("`dump-wave` enabled, waves will be written to \"soc.vcd\".\n");
46-
fp = new VerilatedVcdC;
47-
dut_ptr->trace(fp, 1);
48-
fp->open("soc.vcd");
49-
fp->dump(0);
54+
printf("`dump-wave` enabled, waves will be written to \"soc.wave\".\n");
55+
dutPtr->trace(wavePtr, 1);
56+
wavePtr->open("soc.wave");
57+
wavePtr->dump(0);
5058
}
5159
}
5260
~Emulator()
5361
{
54-
if (args.dump_wave)
62+
if (args.dumpWave)
5563
{
56-
fp->close();
57-
delete fp;
64+
wavePtr->close();
65+
delete wavePtr;
5866
}
5967
}
6068

6169
void step()
6270
{
63-
dut_ptr->clock = 1;
64-
dut_ptr->eval();
71+
dutPtr->clock = 1;
72+
dutPtr->eval();
6573
cycle++;
66-
if (args.dump_wave && args.dump_begin <= cycle && cycle <= args.dump_end)
67-
fp->dump((vluint64_t)cycle);
68-
dut_ptr->clock = 0;
69-
dut_ptr->eval();
74+
if (args.dumpWave && args.dumpBegin <= cycle && cycle <= args.dumpEnd)
75+
{
76+
wavePtr->dump((vluint64_t)cycle);
77+
}
78+
dutPtr->clock = 0;
79+
dutPtr->eval();
7080
}
7181

7282
unsigned long long get_cycle()
@@ -77,7 +87,6 @@ class Emulator
7787
private:
7888
void parseArgs(int argc, char *argv[])
7989
{
80-
8190
int long_index;
8291
const struct option long_options[] = {
8392
{"dump-wave", 0, NULL, 0},
@@ -97,7 +106,7 @@ class Emulator
97106
switch (long_index)
98107
{
99108
case 0:
100-
args.dump_wave = true;
109+
args.dumpWave = true;
101110
continue;
102111
}
103112
// fall through
@@ -108,10 +117,10 @@ class Emulator
108117
args.image = optarg;
109118
break;
110119
case 'b':
111-
args.dump_begin = atoll(optarg);
120+
args.dumpBegin = atoll(optarg);
112121
break;
113122
case 'e':
114-
args.dump_end = atoll(optarg);
123+
args.dumpEnd = atoll(optarg);
115124
break;
116125
}
117126
}
@@ -123,24 +132,33 @@ class Emulator
123132
{
124133
printf("Usage: %s [OPTION...]\n", file);
125134
printf("\n");
126-
printf(" -i, --image=FILE run with this image file\n");
127-
printf(" --dump-wave dump waveform when log is enabled\n");
128-
printf(" -b, --log-begin=NUM display log from NUM th cycle\n");
129-
printf(" -e, --log-end=NUM stop display log at NUM th cycle\n");
130-
printf(" -h, --help print program help info\n");
135+
printf(" -i, --image=FILE run with this image file\n");
136+
printf(" --dump-wave dump vcd(fst) format waveform when log is enabled.\n");
137+
printf(" recommand use fst format, becuase fst format wave\n");
138+
printf(" file is much smaller than vcd format. You need to\n");
139+
printf(" change compiler option in Makefile to switch format.\n");
140+
printf(" -b, --log-begin=NUM display log from NUM th cycle\n");
141+
printf(" -e, --log-end=NUM stop display log at NUM th cycle\n");
142+
printf(" -h, --help print program help info\n");
131143
printf("\n");
132144
}
133145

134146
unsigned long long cycle = 0;
135147

136148
struct Args
137149
{
138-
bool dump_wave = false;
139-
unsigned long dump_begin = 0;
140-
unsigned long dump_end = -1;
150+
bool dumpWave = false;
151+
unsigned long dumpBegin = 0;
152+
unsigned long dumpEnd = -1;
141153
const char *image = nullptr;
142154
} args;
143155

144-
VysyxSoCFull *dut_ptr = nullptr;
145-
VerilatedVcdC *fp = nullptr;
156+
VysyxSoCFull *dutPtr = nullptr;
157+
158+
#ifdef DUMP_WAVE_VCD
159+
VerilatedVcdC *wavePtr = nullptr;
160+
#elif DUMP_WAVE_FST
161+
VerilatedFstC *wavePtr = nullptr;
162+
#endif
163+
146164
};

‎rtl/tc_l2/src/main/scala/axi4/AXI4Bridge.scala‎

Lines changed: 60 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@ package treecorel2
22

33
import chisel3._
44
import chisel3.util._
5+
import treecorel2.common.ConstVal._
56

67
object AXI4Bridge {
78
// Burst types
@@ -62,7 +63,7 @@ object AXI4Bridge {
6263
val SIZE_D = "b11".U(2.W)
6364
}
6465

65-
class AXI4Bridge() extends Module with AXI4Config with InstConfig {
66+
class AXI4Bridge() extends Module with AXI4Config {
6667
val io = IO(new Bundle {
6768
val inst: AXI4USERIO = new AXI4USERIO
6869
val mem: AXI4USERIO = new AXI4USERIO
@@ -283,27 +284,31 @@ class AXI4Bridge() extends Module with AXI4Config with InstConfig {
283284
}
284285

285286
// ------------------Process Data------------------
286-
protected val ALIGNED_WIDTH = 3 // eval: log2(AxiDataWidth / 8)
287-
protected val OFFSET_WIDTH = 6 // eval: log2(AxiDataWidth)
288-
protected val AXI_INST_SIZE = if (SoCEna) 2.U else 3.U // because the flash only support 4 bytes access
289-
protected val AXI_MEM_SIZE = 3.U
290-
protected val MASK_WIDTH = 128 // eval: AxiDataWidth * 2
291-
protected val TRANS_LEN = 1 // eval: 1
292-
protected val BLOCK_TRANS = false.B
293-
294-
// inst data
287+
protected val ALIGNED_INST_WIDTH = log2Ceil(AxiInstDataWidth / 8)
288+
protected val OFFSET_INST_WIDTH = log2Ceil(AxiInstDataWidth)
289+
protected val MASK_INST_WIDTH = AxiInstDataWidth * 2
290+
protected val AXI_INST_SIZE = if (SoCEna) 2.U else 3.U // because the flash only support 4 bytes access
291+
292+
protected val ALIGNED_MEM_WIDTH = log2Ceil(AxiDataWidth / 8)
293+
protected val OFFSET_MEM_WIDTH = log2Ceil(AxiDataWidth)
294+
protected val MASK_MEM_WIDTH = AxiDataWidth * 2
295+
296+
protected val TRANS_LEN = 1 // eval: 1
297+
protected val BLOCK_TRANS = false.B
298+
299+
// ================================inst data=======================
295300
// no-aligned visit
296-
protected val instTransAligned = WireDefault(BLOCK_TRANS || io.inst.addr(ALIGNED_WIDTH - 1, 0) === 0.U)
301+
protected val instTransAligned = WireDefault(BLOCK_TRANS || io.inst.addr(ALIGNED_INST_WIDTH - 1, 0) === 0.U)
297302
protected val instSizeByte = WireDefault(io.inst.size === AXI4Bridge.SIZE_B)
298303
protected val instSizeHalf = WireDefault(io.inst.size === AXI4Bridge.SIZE_H)
299304
protected val instSizeWord = WireDefault(io.inst.size === AXI4Bridge.SIZE_W)
300305
protected val instSizeDouble = WireDefault(io.inst.size === AXI4Bridge.SIZE_D)
301-
// opa: 0100xxx
306+
// opa: 0xxx
302307
// opb: b: 0000
303308
// h: 0001
304309
// w: 0011
305310
// d: 0111
306-
protected val instAddrOpA = WireDefault(UInt(4.W), Cat(0.U, io.inst.addr(ALIGNED_WIDTH - 1, 0)))
311+
protected val instAddrOpA = WireDefault(UInt(4.W), Cat(0.U, io.inst.addr(ALIGNED_INST_WIDTH - 1, 0)))
307312
protected val instAddrOpB = WireDefault(
308313
UInt(4.W),
309314
(Fill(4, instSizeByte) & "b0000".U(4.W))
@@ -313,26 +318,26 @@ class AXI4Bridge() extends Module with AXI4Config with InstConfig {
313318
)
314319

315320
protected val instAddrEnd = WireDefault(UInt(4.W), instAddrOpA + instAddrOpB)
316-
protected val instOverstep = WireDefault(instAddrEnd(3, ALIGNED_WIDTH) =/= 0.U)
321+
protected val instOverstep = WireDefault(instAddrEnd(3, ALIGNED_INST_WIDTH) =/= 0.U)
317322

318323
instAxiLen := Mux(instTransAligned.asBool(), (TRANS_LEN - 1).U, Cat(Fill(7, "b0".U(1.W)), instOverstep))
319324
protected val instAxiSize = AXI_INST_SIZE
320-
protected val instAxiAddr = Cat(io.inst.addr(AxiAddrWidth - 1, ALIGNED_WIDTH), Fill(ALIGNED_WIDTH, "b0".U(1.W)))
321-
protected val instAlignedOffsetLow = Wire(UInt(OFFSET_WIDTH.W))
322-
protected val instAlignedOffsetHig = Wire(UInt(OFFSET_WIDTH.W))
323-
protected val instMask = Wire(UInt(MASK_WIDTH.W))
325+
protected val instAxiAddr = Cat(io.inst.addr(AxiAddrWidth - 1, ALIGNED_INST_WIDTH), Fill(ALIGNED_INST_WIDTH, "b0".U(1.W)))
326+
protected val instAlignedOffsetLow = Wire(UInt(OFFSET_INST_WIDTH.W))
327+
protected val instAlignedOffsetHig = Wire(UInt(OFFSET_INST_WIDTH.W))
328+
protected val instMask = Wire(UInt(MASK_INST_WIDTH.W))
324329

325-
instAlignedOffsetLow := Cat(OFFSET_WIDTH.U - Fill(ALIGNED_WIDTH, "b0".U(1.W)), io.inst.addr(ALIGNED_WIDTH - 1, 0)) << 3
330+
instAlignedOffsetLow := Cat(OFFSET_INST_WIDTH.U - Fill(ALIGNED_INST_WIDTH, "b0".U(1.W)), io.inst.addr(ALIGNED_INST_WIDTH - 1, 0)) << 3
326331
instAlignedOffsetHig := BusWidth.U - instAlignedOffsetLow
327332
instMask := (
328-
(Fill(MASK_WIDTH, instSizeByte) & Cat(Fill(8, "b0".U(1.W)), "hff".U(8.W)))
329-
| (Fill(MASK_WIDTH, instSizeHalf) & Cat(Fill(16, "b0".U(1.W)), "hffff".U(16.W)))
330-
| (Fill(MASK_WIDTH, instSizeWord) & Cat(Fill(32, "b0".U(1.W)), "hffffffff".U(32.W)))
331-
| (Fill(MASK_WIDTH, instSizeDouble) & Cat(Fill(64, "b0".U(1.W)), "hffffffff_ffffffff".U(64.W)))
333+
(Fill(MASK_INST_WIDTH, instSizeByte) & Cat(Fill(8, "b0".U(1.W)), "hff".U(8.W)))
334+
| (Fill(MASK_INST_WIDTH, instSizeHalf) & Cat(Fill(16, "b0".U(1.W)), "hffff".U(16.W)))
335+
| (Fill(MASK_INST_WIDTH, instSizeWord) & Cat(Fill(32, "b0".U(1.W)), "hffffffff".U(32.W)))
336+
| (Fill(MASK_INST_WIDTH, instSizeDouble) & Cat(Fill(64, "b0".U(1.W)), "hffffffff_ffffffff".U(64.W)))
332337
) << instAlignedOffsetLow
333338

334-
protected val instMaskLow = instMask(AxiDataWidth - 1, 0)
335-
protected val instMaskHig = instMask(MASK_WIDTH - 1, AxiDataWidth)
339+
protected val instMaskLow = instMask(AxiInstDataWidth - 1, 0)
340+
protected val instMaskHig = instMask(MASK_INST_WIDTH - 1, AxiInstDataWidth)
336341
protected val instAxiUser = WireDefault(UInt(AxiUserLen.W), Fill(AxiUserLen, "b0".U(1.W)))
337342
protected val instReady = RegInit(false.B)
338343
protected val instReadyNxt = WireDefault(instTransDone)
@@ -352,14 +357,14 @@ class AXI4Bridge() extends Module with AXI4Config with InstConfig {
352357
}
353358
io.inst.resp := instResp
354359

355-
// ================================mem data
356-
protected val memTransAligned = WireDefault(BLOCK_TRANS || io.mem.addr(ALIGNED_WIDTH - 1, 0) === 0.U)
360+
// ================================mem data=======================
361+
protected val memTransAligned = WireDefault(BLOCK_TRANS || io.mem.addr(ALIGNED_MEM_WIDTH - 1, 0) === 0.U)
357362
protected val memSizeByte = WireDefault(io.mem.size === AXI4Bridge.SIZE_B)
358363
protected val memSizeHalf = WireDefault(io.mem.size === AXI4Bridge.SIZE_H)
359364
protected val memSizeWord = WireDefault(io.mem.size === AXI4Bridge.SIZE_W)
360365
protected val memSizeDouble = WireDefault(io.mem.size === AXI4Bridge.SIZE_D)
361366

362-
protected val memAddrOpA = WireDefault(UInt(4.W), Cat(0.U, io.mem.addr(ALIGNED_WIDTH - 1, 0)))
367+
protected val memAddrOpA = WireDefault(UInt(4.W), Cat(0.U, io.mem.addr(ALIGNED_MEM_WIDTH - 1, 0)))
363368
protected val memAddrOpB = WireDefault(
364369
UInt(4.W),
365370
(Fill(4, memSizeByte) & "b0000".U(4.W))
@@ -369,27 +374,40 @@ class AXI4Bridge() extends Module with AXI4Config with InstConfig {
369374
)
370375

371376
protected val memAddrEnd = WireDefault(UInt(4.W), memAddrOpA + memAddrOpB)
372-
protected val memOverstep = WireDefault(memAddrEnd(3, ALIGNED_WIDTH) =/= 0.U)
377+
protected val memOverstep = WireDefault(memAddrEnd(3, ALIGNED_MEM_WIDTH) =/= 0.U)
373378

374379
memAxiLen := Mux(memTransAligned.asBool(), (TRANS_LEN - 1).U, Cat(Fill(7, "b0".U(1.W)), memOverstep))
375380

376-
protected val memAxiSize = AXI_MEM_SIZE
377-
protected val memAxiAddr = Cat(io.mem.addr(AxiAddrWidth - 1, ALIGNED_WIDTH), Fill(ALIGNED_WIDTH, "b0".U(1.W)))
378-
protected val memAlignedOffsetLow = Wire(UInt(OFFSET_WIDTH.W))
379-
protected val memAlignedOffsetHig = Wire(UInt(OFFSET_WIDTH.W))
380-
protected val memMask = Wire(UInt(MASK_WIDTH.W))
381+
// flash only support 4 bytes rd(0x3000_0000~0x3fff_ffff)
382+
// periph suport 4 bytes w/r(0x1000_0000~0x1000_1fff)
383+
// chiplink suport 4 bytes w/r(0x4000_0000~0x7fff_ffff)
384+
protected val memAxiSize = Wire(UInt(3.W))
385+
when(
386+
(io.mem.addr >= UartBaseAddr && io.mem.addr <= UartBoundAddr) ||
387+
(io.mem.addr >= SpiBaseAddr && io.mem.addr <= SpiBoundAddr) ||
388+
(io.mem.addr >= ChiplinkBaseAddr && io.mem.addr <= ChiplinkBoundAddr)
389+
) {
390+
memAxiSize := 2.U
391+
}.otherwise {
392+
memAxiSize := 3.U
393+
}
394+
395+
protected val memAxiAddr = Cat(io.mem.addr(AxiAddrWidth - 1, ALIGNED_MEM_WIDTH), Fill(ALIGNED_MEM_WIDTH, "b0".U(1.W)))
396+
protected val memAlignedOffsetLow = Wire(UInt(OFFSET_MEM_WIDTH.W))
397+
protected val memAlignedOffsetHig = Wire(UInt(OFFSET_MEM_WIDTH.W))
398+
protected val memMask = Wire(UInt(MASK_MEM_WIDTH.W))
381399

382-
memAlignedOffsetLow := Cat(OFFSET_WIDTH.U - Fill(ALIGNED_WIDTH, "b0".U(1.W)), io.mem.addr(ALIGNED_WIDTH - 1, 0)) << 3
400+
memAlignedOffsetLow := Cat(OFFSET_MEM_WIDTH.U - Fill(ALIGNED_MEM_WIDTH, "b0".U(1.W)), io.mem.addr(ALIGNED_MEM_WIDTH - 1, 0)) << 3
383401
memAlignedOffsetHig := BusWidth.U - memAlignedOffsetLow
384402
memMask := (
385-
(Fill(MASK_WIDTH, memSizeByte) & Cat(Fill(8, "b0".U(1.W)), "hff".U(8.W)))
386-
| (Fill(MASK_WIDTH, memSizeHalf) & Cat(Fill(16, "b0".U(1.W)), "hffff".U(16.W)))
387-
| (Fill(MASK_WIDTH, memSizeWord) & Cat(Fill(32, "b0".U(1.W)), "hffffffff".U(32.W)))
388-
| (Fill(MASK_WIDTH, memSizeDouble) & Cat(Fill(64, "b0".U(1.W)), "hffffffff_ffffffff".U(64.W)))
403+
(Fill(MASK_MEM_WIDTH, memSizeByte) & Cat(Fill(8, "b0".U(1.W)), "hff".U(8.W)))
404+
| (Fill(MASK_MEM_WIDTH, memSizeHalf) & Cat(Fill(16, "b0".U(1.W)), "hffff".U(16.W)))
405+
| (Fill(MASK_MEM_WIDTH, memSizeWord) & Cat(Fill(32, "b0".U(1.W)), "hffffffff".U(32.W)))
406+
| (Fill(MASK_MEM_WIDTH, memSizeDouble) & Cat(Fill(64, "b0".U(1.W)), "hffffffff_ffffffff".U(64.W)))
389407
) << memAlignedOffsetLow
390408

391409
protected val memMaskLow = memMask(AxiDataWidth - 1, 0)
392-
protected val memMaskHig = memMask(MASK_WIDTH - 1, AxiDataWidth)
410+
protected val memMaskHig = memMask(MASK_MEM_WIDTH - 1, AxiDataWidth)
393411
protected val memStrb = Wire(UInt((AxiDataWidth / 8).W))
394412

395413
memStrb := (
@@ -399,8 +417,8 @@ class AXI4Bridge() extends Module with AXI4Config with InstConfig {
399417
| ((Fill(8, memSizeDouble) & "b1111_1111".U(8.W)))
400418
)
401419

402-
protected val memStrbLow = WireDefault(UInt((AxiDataWidth / 8).W), memStrb << io.mem.addr(ALIGNED_WIDTH - 1, 0))
403-
protected val memStrbHig = WireDefault(UInt((AxiDataWidth / 8).W), memStrb >> ((AxiDataWidth / 8).U - io.mem.addr(ALIGNED_WIDTH - 1, 0)))
420+
protected val memStrbLow = WireDefault(UInt((AxiDataWidth / 8).W), memStrb << io.mem.addr(ALIGNED_MEM_WIDTH - 1, 0))
421+
protected val memStrbHig = WireDefault(UInt((AxiDataWidth / 8).W), memStrb >> ((AxiDataWidth / 8).U - io.mem.addr(ALIGNED_MEM_WIDTH - 1, 0)))
404422

405423
protected val memAxiUser = Fill(AxiUserLen, "b0".U(1.W))
406424
protected val memReady = RegInit(false.B)

‎rtl/tc_l2/src/main/scala/axi4/AXI4SigBridge.scala‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
// import chisel3.util._
55
// import AXI4Bridge._
66

7-
// class AXI4SigBridge extends Module with AXI4Config with InstConfig {
7+
// class AXI4SigBridge extends Module with AXI4Config {
88
// val io = IO(new Bundle {
99
// val rw: AXI4USERIO = new AXI4USERIO
1010
// val axi: AXI4IO = new AXI4IO

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