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maksyukimaksyuki
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Merge branch 'tc-l2' into dev
2 parents bc18469 + caf7e1b commit 5850590

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8 files changed

+307
-33
lines changed

8 files changed

+307
-33
lines changed

‎.gitignore‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,4 +11,5 @@ ysyxSoC
1111
DRAMsim3
1212
dramsim3.json
1313
dramsim3.txt
14-
dramsim3epoch.json
14+
dramsim3epoch.json
15+
*.vcd

‎rtl/Makefile‎

Lines changed: 55 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,40 @@ DIFFTEST_HOME := $(ROOT_PATH)/difftest
2121
DRAMSIM3_HOME := $(ROOT_PATH)/DRAMsim3
2222
YSYXSOC_HOME := $(ROOT_PATH)/ysyxSoC/ysyx
2323

24+
###### soc var ######
25+
SOC_CSRC_HOME += $(ROOT_PATH)/src/main/csrc
26+
SOC_CSRC_LIB_HOME += $(ROOT_PATH)/ysyxSoC/ysyx/peripheral/spiFlash
27+
SOC_CXXFILES += $(shell find $(SOC_CSRC_HOME) -name "*.cpp")
28+
SOC_CXXFILES += $(shell find $(SOC_CSRC_LIB_HOME) -name "*.cpp")
29+
30+
SOC_VSRC_HOME += $(BUILD_DIR)/soc
31+
SOC_COMPILE_HOME := $(SOC_VSRC_HOME)/emu-compile
32+
SOC_VSRC_TOP := ysyxSoCFull
33+
SOC_VSRC_LIB_HOME += $(ROOT_PATH)/ysyxSoC/ysyx/peripheral/
34+
SOC_VXXFILES += $(shell find $(SOC_VSRC_HOME) -name "*.v")
35+
SOC_VXXFILES += $(shell find $(SOC_VSRC_LIB_HOME) -name "*.v")
36+
37+
SOC_VSRC_INCLPATH += -I$(SOC_VSRC_HOME)
38+
SOC_VSRC_INCLPATH += -I$(ROOT_PATH)/ysyxSoC/ysyx/peripheral/uart16550/rtl
39+
SOC_VSRC_INCLPATH += -I$(ROOT_PATH)/ysyxSoC/ysyx/peripheral/spi/rtl
40+
SOC_CSRC_INCLPATH += -I$(SOC_CSRC_HOME)
41+
SOC_CSRC_INCLPATH += -I$(SOC_CSRC_LIB_HOME)
42+
43+
SOC_CXXFLAGS += -std=c++11 -static -Wall $(SOC_CSRC_INCLPATH)
44+
SOC_FLAGS += --cc --exe --top-module $(SOC_VSRC_TOP)
45+
SOC_FLAGS += --x-assign unique -O3 -CFLAGS "$(SOC_CXXFLAGS)"
46+
SOC_FLAGS += --trace --assert --stats-vars --output-split 30000 --output-split-cfuncs 30000
47+
SOC_FLAGS += --timescale "1ns/1ns" -Wno-fatal --trace
48+
SOC_FLAGS += -o $(BUILD_DIR)/soc/emu
49+
SOC_FLAGS += -Mdir $(BUILD_DIR)/soc/emu-compile
50+
SOC_FLAGS += $(SOC_VSRC_INCLPATH) $(SOC_CXXFILES) $(SOC_VXXFILES)
51+
52+
CCACHE := $(if $(shell which ccache),ccache,)
53+
ifneq ($(CCACHE),)
54+
export OBJCACHE = ccache
55+
endif
56+
57+
2458
export AM_HOME := $(AM_FOLDER_PATH)/abstract-machine
2559
export NEMU_HOME := $(ROOT_PATH)/NEMU
2660
export NOOP_HOME := $(ROOT_PATH)
@@ -80,7 +114,7 @@ difftestBuild:
80114
@sed -i 's/io_memAXI_0_\([a-z]*\)_bits_data,/io_memAXI_0_\1_bits_data[3:0],/g' $(BUILD_DIR)/SimTop.v
81115
@sed -i 's/io_memAXI_0_w_bits_data =/io_memAXI_0_w_bits_data[0] =/g' $(BUILD_DIR)/SimTop.v
82116
@sed -i 's/ io_memAXI_0_r_bits_data;/ io_memAXI_0_r_bits_data[0];/g' $(BUILD_DIR)/SimTop.v
83-
$(MAKE) -C $(DIFFTEST_HOME) WITH_DRAMSIM3=1
117+
$(MAKE) -C $(DIFFTEST_HOME) WITH_DRAMSIM3=1 EMU_TRACE=1
84118

85119
diffAllBuild: diffBuild difftestBuild
86120

@@ -185,17 +219,18 @@ $(cpuTestCaseName): cputest-%: $(CPUTEST_HOME)/build/%-riscv64-mycpu.bin
185219

186220
###### soc name rule test target ######
187221
socTopModify:
188-
@cp $(BUILD_DIR)/SoCTop.v $(BUILD_DIR)/ysyx_210324.v
189-
@sed -i 's/module ysyx_210324_SoCTop/module ysyx_210324/g' $(BUILD_DIR)/ysyx_210324.v
190-
@sed -i 's/io_\([a-z]*\)_\([a-z]*\)_[bits]*_*\([a-z]*\)/io_\1_\2\3/g' $(BUILD_DIR)/ysyx_210324.v
222+
@mkdir -p $(BUILD_DIR)/soc
223+
@cp $(BUILD_DIR)/SoCTop.v $(BUILD_DIR)/soc/ysyx_210324.v
224+
@sed -i 's/module ysyx_210324_SoCTop/module ysyx_210324/g' $(BUILD_DIR)/soc/ysyx_210324.v
225+
@sed -i 's/io_\([a-z]*\)_\([a-z]*\)_[bits]*_*\([a-z]*\)/io_\1_\2\3/g' $(BUILD_DIR)/soc/ysyx_210324.v
191226

192227
# FIMXE: need a better solution, not just copy to dir everytime
193228
socNameCheck: socTopModify
194-
@cp $(YSYXSOC_HOME)/soc/cpu-check.py $(BUILD_DIR)
195-
@cd $(BUILD_DIR) && echo 324 | python3 cpu-check.py
229+
@cp $(YSYXSOC_HOME)/soc/cpu-check.py $(BUILD_DIR)/soc
230+
@cd $(BUILD_DIR)/soc && echo 324 | python3 cpu-check.py
196231

197232
socLintCheck: socNameCheck
198-
@cp $(BUILD_DIR)/ysyx_210324.v $(YSYXSOC_HOME)/lint/
233+
@cp $(BUILD_DIR)/soc/ysyx_210324.v $(YSYXSOC_HOME)/lint/
199234
@sed -i 's/ID = \([0-9]*\)/ID = 210324/g' $(YSYXSOC_HOME)/lint/Makefile
200235
@echo -e "\033[1;32mstart lint check....\033[0m"
201236
$(MAKE) -C $(YSYXSOC_HOME)/lint/ lint
@@ -204,6 +239,18 @@ socLintCheck: socNameCheck
204239
$(MAKE) -C $(YSYXSOC_HOME)/lint/ lint-unused
205240
@echo -e "\033[1;32mlint-unused check done\033[0m"
206241

242+
socPrevBuild:
243+
# FIXME: if only need to moidfy core, commit it
244+
# @cp $(YSYXSOC_HOME)/soc/ysyxSoCFull.v $(BUILD_DIR)/soc
245+
@sed -i s/ysyx_000000/ysyx_210324/g $(BUILD_DIR)/soc/ysyxSoCFull.v
246+
verilator $(SOC_FLAGS)
247+
248+
socBuild: socPrevBuild
249+
$(MAKE) VM_PARALLEL_BUILDS=1 OPT_FAST="-O3" -C $(SOC_COMPILE_HOME) -f V$(SOC_VSRC_TOP).mk
250+
251+
socSimRun:
252+
$(SOC_VSRC_HOME)/emu -i $(YSYXSOC_HOME)/program/bin/flash/hello-flash.bin --dump-wave
253+
207254
###### clean target ######
208255
cleanBuild:
209256
rm -rf $(BUILD_DIR)
@@ -219,5 +266,5 @@ cleanAll: cleanBuild cleanMillOut cleanDepRepo
219266

220267
.PHONY: millTest diffBuild help compile bsp reformat checkformat \
221268
nemuBuild difftestBuild riscvTestBuild cpuTestBuild amTestBuild demoTest \
222-
socTopModify socNameCheck \
269+
socTopModify socNameCheck socBuild\
223270
cleanBuild cleanMillOut cleanDepRepo cleanAll

‎rtl/tc_l2/src/main/csrc/emu.h‎

Lines changed: 146 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,146 @@
1+
#include <unistd.h>
2+
#include <getopt.h>
3+
4+
#include <verilated_vcd_c.h>
5+
#include <verilated.h>
6+
#include <VysyxSoCFull.h>
7+
8+
extern "C"
9+
{
10+
void flash_init(const char *img);
11+
}
12+
13+
class Emulator
14+
{
15+
public:
16+
Emulator(int argc, char *argv[])
17+
{
18+
parseArgs(argc, argv);
19+
20+
if (args.image == nullptr)
21+
{
22+
printf("Image file unspecified. Use -i to provide the image of flash");
23+
exit(1);
24+
}
25+
printf("Initializing flash with \"%s\" ...\n", args.image);
26+
flash_init(args.image);
27+
28+
printf("Initializing and resetting DUT ...\n");
29+
dut_ptr = new VysyxSoCFull;
30+
dut_ptr->reset = 1;
31+
for (int i = 0; i < 10; i++)
32+
{
33+
dut_ptr->clock = 0;
34+
dut_ptr->eval();
35+
dut_ptr->clock = 1;
36+
dut_ptr->eval();
37+
}
38+
dut_ptr->clock = 0;
39+
dut_ptr->reset = 0;
40+
dut_ptr->eval();
41+
42+
if (args.dump_wave)
43+
{
44+
Verilated::traceEverOn(true);
45+
printf("`dump-wave` enabled, waves will be written to \"soc.vcd\".\n");
46+
fp = new VerilatedVcdC;
47+
dut_ptr->trace(fp, 1);
48+
fp->open("soc.vcd");
49+
fp->dump(0);
50+
}
51+
}
52+
~Emulator()
53+
{
54+
if (args.dump_wave)
55+
{
56+
fp->close();
57+
delete fp;
58+
}
59+
}
60+
61+
void step()
62+
{
63+
dut_ptr->clock = 1;
64+
dut_ptr->eval();
65+
cycle++;
66+
if (args.dump_wave && args.dump_begin <= cycle && cycle <= args.dump_end)
67+
fp->dump((vluint64_t)cycle);
68+
dut_ptr->clock = 0;
69+
dut_ptr->eval();
70+
}
71+
72+
unsigned long long get_cycle()
73+
{
74+
return cycle;
75+
}
76+
77+
private:
78+
void parseArgs(int argc, char *argv[])
79+
{
80+
81+
int long_index;
82+
const struct option long_options[] = {
83+
{"dump-wave", 0, NULL, 0},
84+
{"log-begin", 1, NULL, 'b'},
85+
{"log-end", 1, NULL, 'e'},
86+
{"image", 1, NULL, 'i'},
87+
{"help", 0, NULL, 'h'},
88+
{0, 0, NULL, 0}};
89+
90+
int o;
91+
while ((o = getopt_long(argc, const_cast<char *const *>(argv),
92+
"-hi:b:e:", long_options, &long_index)) != -1)
93+
{
94+
switch (o)
95+
{
96+
case 0:
97+
switch (long_index)
98+
{
99+
case 0:
100+
args.dump_wave = true;
101+
continue;
102+
}
103+
// fall through
104+
default:
105+
print_help(argv[0]);
106+
exit(0);
107+
case 'i':
108+
args.image = optarg;
109+
break;
110+
case 'b':
111+
args.dump_begin = atoll(optarg);
112+
break;
113+
case 'e':
114+
args.dump_end = atoll(optarg);
115+
break;
116+
}
117+
}
118+
119+
Verilated::commandArgs(argc, argv);
120+
}
121+
122+
static inline void print_help(const char *file)
123+
{
124+
printf("Usage: %s [OPTION...]\n", file);
125+
printf("\n");
126+
printf(" -i, --image=FILE run with this image file\n");
127+
printf(" --dump-wave dump waveform when log is enabled\n");
128+
printf(" -b, --log-begin=NUM display log from NUM th cycle\n");
129+
printf(" -e, --log-end=NUM stop display log at NUM th cycle\n");
130+
printf(" -h, --help print program help info\n");
131+
printf("\n");
132+
}
133+
134+
unsigned long long cycle = 0;
135+
136+
struct Args
137+
{
138+
bool dump_wave = false;
139+
unsigned long dump_begin = 0;
140+
unsigned long dump_end = -1;
141+
const char *image = nullptr;
142+
} args;
143+
144+
VysyxSoCFull *dut_ptr = nullptr;
145+
VerilatedVcdC *fp = nullptr;
146+
};

‎rtl/tc_l2/src/main/csrc/main.cpp‎

Lines changed: 57 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,57 @@
1+
#include <cstdio>
2+
#include <csignal>
3+
#include <chrono>
4+
namespace chrono = std::chrono;
5+
6+
#include "verilated.h" //Defines common routines
7+
#include "VysyxSoCFull.h"
8+
9+
#include <emu.h>
10+
11+
static int signal_received = 0;
12+
13+
void sig_handler(int signo)
14+
{
15+
if (signal_received != 0)
16+
{
17+
puts("SIGINT received, forcely shutting down.\n");
18+
exit(0);
19+
}
20+
puts("SIGINT received, gracefully shutting down... Type Ctrl+C again to stop forcely.\n");
21+
signal_received = signo;
22+
}
23+
24+
static Emulator *emu = nullptr;
25+
chrono::system_clock::time_point sim_start_time;
26+
void release()
27+
{
28+
if (emu != nullptr)
29+
{
30+
auto elapsed = chrono::duration_cast<chrono::seconds>(chrono::system_clock::now() - sim_start_time);
31+
printf("Simulated %llu cycles in %lds\n",
32+
emu->get_cycle(),
33+
elapsed.count());
34+
delete emu;
35+
}
36+
}
37+
38+
int main(int argc, char *argv[])
39+
{
40+
printf("Emu compiled at %s, %s\n", __DATE__, __TIME__);
41+
42+
if (signal(SIGINT, sig_handler) == SIG_ERR)
43+
{
44+
printf("can't catch SIGINT\n");
45+
}
46+
atexit(release);
47+
48+
emu = new Emulator(argc, argv);
49+
printf("Start simulating ...\n");
50+
sim_start_time = chrono::system_clock::now();
51+
while (!Verilated::gotFinish() && signal_received == 0)
52+
{
53+
emu->step();
54+
}
55+
56+
return 0;
57+
}

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