feat: make axi4 config extend from inst config

Author: maksyuki

rtl/tc_l2/src/main/scala/common/AXI4Config.scala

@@ -2,23 +2,23 @@ package treecorel2
 
 import chisel3._
 import chisel3.util._
-
 //AXI parameters
-trait AXI4Config {
+trait AXI4Config extends InstConfig {
   val AxiReqLen = 2
   val AxiReqRd  = 0
   val AxiReqWt  = 1
   val AxiReqNop = 2
 
-  val AxiDataWidth = 64
-  val AxiAddrWidth = 32 // FIME: is right? the original val is 64
-  val AxiProtLen   = 3
-  val AxiIdLen     = 4
-  val AxiUserLen   = 1
-  val AxiSizeLen   = 2
-  val AxiBurstLen  = 2
-  val AxiCacheLen  = 4
-  val AxiQosLen    = 4
-  val AxiRegionLen = 4
-  val AxiRespLen   = 2
+  val AxiDataWidth     = 64
+  val AxiInstDataWidth = if (SoCEna) 32 else 64
+  val AxiAddrWidth     = 32 // FIME: is right? the original val is 64
+  val AxiProtLen       = 3
+  val AxiIdLen         = 4
+  val AxiUserLen       = 1
+  val AxiSizeLen       = 2
+  val AxiBurstLen      = 2
+  val AxiCacheLen      = 4
+  val AxiQosLen        = 4
+  val AxiRegionLen     = 4
+  val AxiRespLen       = 2
 }

rtl/tc_l2/src/main/scala/core/TreeCoreL2.scala

@@ -3,7 +3,7 @@ package treecorel2
 import chisel3._
 import difftest._
 
-class TreeCoreL2() extends Module with AXI4Config with InstConfig {
+class TreeCoreL2() extends Module with AXI4Config {
   val io = IO(new Bundle {
     val inst: AXI4USERIO = Flipped(new AXI4USERIO)
     val mem:  AXI4USERIO = Flipped(new AXI4USERIO)

rtl/tc_l2/src/main/scala/core/inst/PCReg.scala

@@ -3,7 +3,7 @@ package treecorel2
 import chisel3._
 import AXI4Bridge._
 
-class PCReg() extends Module with AXI4Config with InstConfig {
+class PCReg() extends Module with AXI4Config {
   val io = IO(new Bundle {
     val axi:         AXI4USERIO = Flipped(new AXI4USERIO) // from axi
     val ctrl2pc:     CTRL2PCIO  = Flipped(new CTRL2PCIO) // from ctrl

rtl/tc_l2/src/main/scala/core/ma/MemoryAccessStage.scala

@@ -8,7 +8,7 @@ import treecorel2.common.{getSignExtn, getZeroExtn}
 
 // read data addr is calc by alu
 // write data addr is passed from id stage directly
-class MemoryAccessStage extends Module with AXI4Config with InstConfig {
+class MemoryAccessStage extends Module with AXI4Config {
   val io = IO(new Bundle {
     // wt mem ena signal is send from ex2ma stage
     // example: sd -> M[x[rs1]+ sext(offset)] = x[rs2][7:0]

rtl/tc_l2/src/main/scala/top/SimTop.scala

@@ -4,7 +4,7 @@ import chisel3._
 import treecorel2._
 import difftest._
 
-class SimTop() extends Module with AXI4Config with InstConfig {
+class SimTop() extends Module with AXI4Config {
   val io = IO(new Bundle {
     val logCtrl  = new LogCtrlIO
     val perfInfo = new PerfInfoIO

rtl/tc_l2/src/main/scala/top/SoCTop.scala

@@ -4,7 +4,7 @@ import chisel3._
 import treecorel2._
 import difftest._
 
-class SoCTop() extends Module with AXI4Config with InstConfig {
+class SoCTop() extends Module with AXI4Config {
   val io = IO(new Bundle {
     val interrupt = Input(Bool())
     val master    = new SOCAXI4IO