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maksyukimaksyuki
committed
refactor: delete commit, surplus var and add some debug code
1 parent fc6a977 commit caf7e1b

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2 files changed

+41
-21
lines changed

2 files changed

+41
-21
lines changed

‎rtl/tc_l2/src/main/scala/axi4/AXI4Bridge.scala‎

Lines changed: 41 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -285,7 +285,8 @@ class AXI4Bridge() extends Module with AXI4Config with InstConfig {
285285
// ------------------Process Data------------------
286286
protected val ALIGNED_WIDTH = 3 // eval: log2(AxiDataWidth / 8)
287287
protected val OFFSET_WIDTH = 6 // eval: log2(AxiDataWidth)
288-
protected val AXI_SIZE = if (SoCEna) 2.U else 3.U // eval: log2(AxiDataWidth / 8)
288+
protected val AXI_INST_SIZE = if (SoCEna) 2.U else 3.U // because the flash only support 4 bytes access
289+
protected val AXI_MEM_SIZE = 3.U
289290
protected val MASK_WIDTH = 128 // eval: AxiDataWidth * 2
290291
protected val TRANS_LEN = 1 // eval: 1
291292
protected val BLOCK_TRANS = false.B
@@ -315,8 +316,7 @@ class AXI4Bridge() extends Module with AXI4Config with InstConfig {
315316
protected val instOverstep = WireDefault(instAddrEnd(3, ALIGNED_WIDTH) =/= 0.U)
316317

317318
instAxiLen := Mux(instTransAligned.asBool(), (TRANS_LEN - 1).U, Cat(Fill(7, "b0".U(1.W)), instOverstep))
318-
// TODO: bug?
319-
protected val instAxiSize = AXI_SIZE(2, 0);
319+
protected val instAxiSize = AXI_INST_SIZE
320320
protected val instAxiAddr = Cat(io.inst.addr(AxiAddrWidth - 1, ALIGNED_WIDTH), Fill(ALIGNED_WIDTH, "b0".U(1.W)))
321321
protected val instAlignedOffsetLow = Wire(UInt(OFFSET_WIDTH.W))
322322
protected val instAlignedOffsetHig = Wire(UInt(OFFSET_WIDTH.W))
@@ -325,10 +325,10 @@ class AXI4Bridge() extends Module with AXI4Config with InstConfig {
325325
instAlignedOffsetLow := Cat(OFFSET_WIDTH.U - Fill(ALIGNED_WIDTH, "b0".U(1.W)), io.inst.addr(ALIGNED_WIDTH - 1, 0)) << 3
326326
instAlignedOffsetHig := BusWidth.U - instAlignedOffsetLow
327327
instMask := (
328-
(Fill(MASK_WIDTH, instSizeByte) & Cat(MASK_WIDTH.U - Fill(8, "b0".U(1.W)), "hff".U(8.W)))
329-
| (Fill(MASK_WIDTH, instSizeHalf) & Cat(MASK_WIDTH.U - Fill(16, "b0".U(1.W)), "hffff".U(16.W)))
330-
| (Fill(MASK_WIDTH, instSizeWord) & Cat(MASK_WIDTH.U - Fill(32, "b0".U(1.W)), "hffffffff".U(32.W)))
331-
| (Fill(MASK_WIDTH, instSizeDouble) & Cat(MASK_WIDTH.U - Fill(64, "b0".U(1.W)), "hffffffff_ffffffff".U(64.W)))
328+
(Fill(MASK_WIDTH, instSizeByte) & Cat(Fill(8, "b0".U(1.W)), "hff".U(8.W)))
329+
| (Fill(MASK_WIDTH, instSizeHalf) & Cat(Fill(16, "b0".U(1.W)), "hffff".U(16.W)))
330+
| (Fill(MASK_WIDTH, instSizeWord) & Cat(Fill(32, "b0".U(1.W)), "hffffffff".U(32.W)))
331+
| (Fill(MASK_WIDTH, instSizeDouble) & Cat(Fill(64, "b0".U(1.W)), "hffffffff_ffffffff".U(64.W)))
332332
) << instAlignedOffsetLow
333333

334334
protected val instMaskLow = instMask(AxiDataWidth - 1, 0)
@@ -373,7 +373,7 @@ class AXI4Bridge() extends Module with AXI4Config with InstConfig {
373373

374374
memAxiLen := Mux(memTransAligned.asBool(), (TRANS_LEN - 1).U, Cat(Fill(7, "b0".U(1.W)), memOverstep))
375375

376-
protected val memAxiSize = AXI_SIZE(2, 0);
376+
protected val memAxiSize = AXI_MEM_SIZE
377377
protected val memAxiAddr = Cat(io.mem.addr(AxiAddrWidth - 1, ALIGNED_WIDTH), Fill(ALIGNED_WIDTH, "b0".U(1.W)))
378378
protected val memAlignedOffsetLow = Wire(UInt(OFFSET_WIDTH.W))
379379
protected val memAlignedOffsetHig = Wire(UInt(OFFSET_WIDTH.W))
@@ -382,10 +382,10 @@ class AXI4Bridge() extends Module with AXI4Config with InstConfig {
382382
memAlignedOffsetLow := Cat(OFFSET_WIDTH.U - Fill(ALIGNED_WIDTH, "b0".U(1.W)), io.mem.addr(ALIGNED_WIDTH - 1, 0)) << 3
383383
memAlignedOffsetHig := BusWidth.U - memAlignedOffsetLow
384384
memMask := (
385-
(Fill(MASK_WIDTH, memSizeByte) & Cat(MASK_WIDTH.U - Fill(8, "b0".U(1.W)), "hff".U(8.W)))
386-
| (Fill(MASK_WIDTH, memSizeHalf) & Cat(MASK_WIDTH.U - Fill(16, "b0".U(1.W)), "hffff".U(16.W)))
387-
| (Fill(MASK_WIDTH, memSizeWord) & Cat(MASK_WIDTH.U - Fill(32, "b0".U(1.W)), "hffffffff".U(32.W)))
388-
| (Fill(MASK_WIDTH, memSizeDouble) & Cat(MASK_WIDTH.U - Fill(64, "b0".U(1.W)), "hffffffff_ffffffff".U(64.W)))
385+
(Fill(MASK_WIDTH, memSizeByte) & Cat(Fill(8, "b0".U(1.W)), "hff".U(8.W)))
386+
| (Fill(MASK_WIDTH, memSizeHalf) & Cat(Fill(16, "b0".U(1.W)), "hffff".U(16.W)))
387+
| (Fill(MASK_WIDTH, memSizeWord) & Cat(Fill(32, "b0".U(1.W)), "hffffffff".U(32.W)))
388+
| (Fill(MASK_WIDTH, memSizeDouble) & Cat(Fill(64, "b0".U(1.W)), "hffffffff_ffffffff".U(64.W)))
389389
) << memAlignedOffsetLow
390390

391391
protected val memMaskLow = memMask(AxiDataWidth - 1, 0)
@@ -508,12 +508,19 @@ class AXI4Bridge() extends Module with AXI4Config with InstConfig {
508508
for (i <- 0 until TRANS_LEN) {
509509
when(rdHdShk && io.axi.r.bits.id === instAxiId) {
510510
when((~instTransAligned) && instOverstep) {
511+
printf("inst not aligned!!!!!!\n")
511512
when(instTransLen(0, 0) =/= 0.U) {
512513
instDataReadReg := instDataReadReg | axiRdDataHig
513514
}.otherwise {
514515
instDataReadReg := axiRdDataLow
515516
}
516517
}.elsewhen(instTransLen === i.U) {
518+
// printf("inst rdata align!!!!!!!!!!!!!!!!!!!!!!!!!!!\n")
519+
// printf(p"[axi4]instAlignedOffsetLow = 0x${Hexadecimal(instAlignedOffsetLow)}\n")
520+
// printf(p"[axi4]instAlignedOffsetHig = 0x${Hexadecimal(instAlignedOffsetHig)}\n")
521+
// printf(p"[axi4]instMask = 0x${Hexadecimal(instMask)}\n")
522+
// printf(p"[axi4]instMaskLow = 0x${Hexadecimal(instMaskLow)}\n")
523+
// printf(p"[axi4]instMaskHig = 0x${Hexadecimal(instMaskHig)}\n\n")
517524
instDataReadReg := axiRdDataLow
518525
}
519526
}
@@ -526,21 +533,35 @@ class AXI4Bridge() extends Module with AXI4Config with InstConfig {
526533
when((~memTransAligned) && memOverstep) {
527534
when(memTransLen(0, 0) =/= 0.U) {
528535
memDataReadReg := memDataReadReg | axiRdDataHig
529-
// printf("rdata hig!!!!!!!!!!!!!!!!!!!!!!!!!!!\n")
530-
// printf(p"[axi4]memMask = 0x${Hexadecimal(memMask)}\n")
531-
// printf(p"[axi4]memMaskHig = 0x${Hexadecimal(memMaskHig)}\n")
532-
536+
// printf("mem rdata hig!!!!!!!!!!!!!!!!!!!!!!!!!!!\n")
533537
// printf(p"[axi4]memAlignedOffsetLow = 0x${Hexadecimal(memAlignedOffsetLow)}\n")
534538
// printf(p"[axi4]memAlignedOffsetHig = 0x${Hexadecimal(memAlignedOffsetHig)}\n")
535-
// printf(p"[axi4]axiRdDataHig = 0x${Hexadecimal(axiRdDataHig)}\n")
536-
// printf(p"[axi4]memDataReadReg = 0x${Hexadecimal(memDataReadReg)}\n")
539+
// printf(p"[axi4]memMask = 0x${Hexadecimal(memMask)}\n")
540+
// printf(p"[axi4]memMaskLow = 0x${Hexadecimal(memMaskLow)}\n")
541+
// printf(p"[axi4]memMaskHig = 0x${Hexadecimal(memMaskHig)}\n")
542+
// printf(p"[axi4]io.axi.r.bits.data = 0x${Hexadecimal(io.axi.r.bits.data)}\n")
543+
// printf(p"[axi4]axiRdDataHig = 0x${Hexadecimal(axiRdDataHig)}\n\n")
537544
}.otherwise {
538545
memDataReadReg := axiRdDataLow
539-
// printf("rdata low!!!!!!!!!!!!!!!!!!!!!!!!!!!\n")
546+
// printf("mem rdata low!!!!!!!!!!!!!!!!!!!!!!!!!!!\n")
547+
// printf(p"[axi4]memAlignedOffsetLow = 0x${Hexadecimal(memAlignedOffsetLow)}\n")
548+
// printf(p"[axi4]memAlignedOffsetHig = 0x${Hexadecimal(memAlignedOffsetHig)}\n")
549+
// printf(p"[axi4]memMask = 0x${Hexadecimal(memMask)}\n")
550+
// printf(p"[axi4]memMaskLow = 0x${Hexadecimal(memMaskLow)}\n")
551+
// printf(p"[axi4]memMaskHig = 0x${Hexadecimal(memMaskHig)}\n")
552+
// printf(p"[axi4]io.axi.r.bits.data = 0x${Hexadecimal(io.axi.r.bits.data)}\n")
553+
// printf(p"[axi4]axiRdDataLow = 0x${Hexadecimal(axiRdDataLow)}\n\n")
540554
}
541555
}.elsewhen(memTransLen === i.U) {
542556
memDataReadReg := axiRdDataLow
543-
// printf("rdata norm!!!!!!!!!!!!!!!!!!!!!!!!!!!\n")
557+
// printf("mem rdata align!!!!!!!!!!!!!!!!!!!!!!!!!!!\n")
558+
// printf(p"[axi4]memAlignedOffsetLow = 0x${Hexadecimal(memAlignedOffsetLow)}\n")
559+
// printf(p"[axi4]memAlignedOffsetHig = 0x${Hexadecimal(memAlignedOffsetHig)}\n")
560+
// printf(p"[axi4]memMask = 0x${Hexadecimal(memMask)}\n")
561+
// printf(p"[axi4]memMaskLow = 0x${Hexadecimal(memMaskLow)}\n")
562+
// printf(p"[axi4]memMaskHig = 0x${Hexadecimal(memMaskHig)}\n")
563+
// printf(p"[axi4]io.axi.r.bits.data = 0x${Hexadecimal(io.axi.r.bits.data)}\n")
564+
// printf(p"[axi4]axiRdDataLow = 0x${Hexadecimal(axiRdDataLow)}\n\n")
544565
}
545566
}
546567
}

‎rtl/tc_l2/src/main/scala/core/inst/PCReg.scala‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,6 @@ class PCReg() extends Module with AXI4Config with InstConfig {
2222
io.axi.resp := DontCare
2323
io.axi.addr := pc
2424
io.axi.id := 0.U
25-
// io.axi.valid := true.B // TODO: need to judge when mem need to read
2625
io.axi.valid := ~io.ctrl2pc.maStall // TODO: maybe this code lead to cycle
2726
io.axi.size := AXI4Bridge.SIZE_W
2827

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