Merge branch 'tc-l2' into dev

Author: maksyuki

README.md

@@ -1,7 +1,7 @@
 <p align="center">
     <img width="200px" src="./.images/tree_core_logo.svg" align="center" alt="Tree Core CPU" />
     <h1 align="center">TreeCore CPU</h1>
-    <p align="center">A series of RISC-V soft core processor written from scratch</p>
+    <p align="center">A series of RISCV soft core processor written from scratch</p>
 </p>
 <p align="center">
     <a href="./LICENSE">
@@ -19,25 +19,34 @@
 </p>
 
 ## Overview
-the TreeCore L2 is the 
+the TreeCore L2 is the riscv64 software core developed under the [Open Source Chip Project by University (OSCPU)](https://github.com/OSCPU). OSCPU was initiated by ICTCAS(**_Institute of computing Technology, Chinese Academy of Sciences_**), which aims to make students use all open-source toolchain to design, develop open-source chips by themselves. It also can be called "One Life, One Chip" project in Chinese which has achieved two season. Now Season 3 is in progress in 2021.
 
 ## Feature
-* 64-bit five-stage pipeline RISC-V ISA CPU core.
-* support RISC-V integer(I) instruction set.
+* 64-bits single-issue, five-stage pipeline RISCV ISA CPU core.
+* support RISCV integer(I) instruction set.
 * supports machine mode privilege levels.
 * supports AXI4 inst and mem acess.
 * can boot rt-thread.
+* develop under all open-source toolchain.
 
+## Develop Schedule
+Now, the develop schedule is recorded by the **Tencent Document**. You can click this link [schedule table](https://docs.qq.com/sheet/DY3lORW5Pa3pLRFpT?newPad=1&newPadType=clone&tab=BB08J2) to view it.
 
 ## Datapath Diagram
 
 ### Memory Map
 
 | Range                     | Description                                         |
 | ------------------------- | --------------------------------------------------- |
-| 0x0000_0000 - 0x0000_ffff | 64KB TCM Memory                                     |
-| 0x0000_2000               | Boot address (configurable, see RISCV_BOOT_ADDRESS) |
-| 0x8000_0000 - 0xffff_ffff | Peripheral address space (from AXI4-L port)         |
+| 0x0000_0000 - 0x01ff_ffff | reserve                                             |
+| 0x0200_0000 - 0x0200_ffff | clint                                               |
+| 0x0201_0000 - 0x0fff_ffff | reserve                                             |
+| 0x1000_0000 - 0x1000_0fff | uart16550                                           |
+| 0x1000_1000 - 0x1000_1fff | spi controller                                      |
+| 0x1000_2000 - 0x2fff_ffff | reserve                                             |
+| 0x3000_0000 - 0x3fff_ffff | spi flash xip mode                                  |
+| 0x4000_0000 - 0x7fff_ffff | chiplink                                            |
+| 0x8000_0000 - 0x8xxx_xxxx | mem                                                 |
 
 #### Configuration
 
@@ -83,7 +92,8 @@ $ make demoTest
 ## License
 
 ## Story
+I heard the word **_RISCV_** first time in the second semester of my junior year(that is, the summer of 2016). My roommate participated in the pilot class of "Computer Architecture" organized by the college, and **their task was to design a simple soft-core CPU based on the RISCV instruction set**. At that time, I only knew that it was an open source RISC instruction set launched by the University of Berkeley. I felt that it was similar to the MIPS, so I didn't take it too seriously. But what is unexpected is that after just a few period of development, the RISCV has been supported by many Internet and semiconductor giants around the world, and more and more research institutions, start-ups begin to design their own proprietary processors based on it. Although now the performance and application of RISCV are still limited, **I believe RISCV will usher in a revolution that can change the old pattern in someday**. 
 
-I heard the word RISC-V for the first time in the second semester of my junior year (that is, the summer of 2016), my roommate happened to participate in the pilot class of "Computer Architecture" organized by the college, and **their task was to design a simple soft-core CPU based on the RISC-V instruction set**. At that time, I only knew that it was an open source RISC instruction set launched by the University of Berkeley, I felt that it was similar to the MIPS instruction set used in our ordinary classes, so I didn't take it too seriously. But what is unexpected is that after just a few years of development, the RISC-V instruction set has been supported by many Internet and semiconductor giants around the world, and more and more research institutions and start-ups begin to design their own proprietary processors based on it. I think the current RISC-V is just like the early Linux kernel, although the function and performance are still very limited, with the power of open source collaboration, **I believe RISC-V will one day usher in a revolution that can change the old pattern in some areas**. Therefore, in order not to be abandoned by the coming new era, as an amateur hardware enthusiast, I think it is necessary for me to learn the RISC-V instruction set, maybe I will have the opportunity to contribute to the design and R & D of domestic independent controllable processor in the future!
+The ancients once said: **it’s always shallow on paper, and you must do it yourself**. For the learn of the computer architecture, there is no better way to realize it from scratch. So I started to collect materials from the Internet, and I found the learning threshold and cost is very high. In addition, in order to pursue the performance, some open-source CPU cores are very complex(such as using mulit-pipelines, multi-core processing, out-of-order execution technology, etc), it is very difficult for beginners to get started. So I decided to design a series of open source processors from scratch, which has **simple, understandable architecture, high-quality code with step-to-step tutorial**. 
 
-The ancients once said: **it’s always shallow on paper, and you must do it yourself**, since you decide to learn RISC-V, you must practice it to understand it. For this kind of project at the bottom of computer architecture, there is no better way than to realize it from scratch. So with this idea, I started to collect information on the Internet, and the results were disappointing. Although there are many foreign open source projects related to RISC-V, many of them are implemented using Chisel, a high-level hardware construction language. The learning threshold is very high. In addition, in order to pursue the overall performance, some CPU system architectures are designed to be very complex (such as using five-level or more pipelines, multi-core processing, out-of-order execution, etc), it is very difficult for beginners to get started. So after careful consideration,  I decided to write an open source processor project from scratch, which has a **simple system architecture, clear code and excellent package**, I hope it can be like Arduino, which stands out from many microcontrollers, so that more hardware enthusiasts can quickly start to experience, and develop many interesting applications based on it. In the future, under the mutual promotion of the software and hardware ecological environment, maybe more people will like CPU development and be willing to spend time on it. If I can really do this, I will be satisfied.
+I hope it can become a ABC project like Arduino and make more processor enthusiasts or computer related specialized students enter into the computer architecture field. In the future, under the mutual promotion of the software and hardware ecosystem, I believe more people will like CPU development and be willing to spend time on it. 

rtl/tc_l2/src/main/scala/axi4/AXI4Bridge.scala

@@ -302,7 +302,7 @@ class AXI4Bridge() extends Module with AXI4Config with InstConfig {
   //      h: 0001
   //      w: 0011
   //      d: 0111
-  protected val instAddrOpA = WireDefault(UInt(4.W), Cat(0.U, io.inst.addr(ALIGNED_WIDTH-1, 0)))
+  protected val instAddrOpA = WireDefault(UInt(4.W), Cat(0.U, io.inst.addr(ALIGNED_WIDTH - 1, 0)))
   protected val instAddrOpB = WireDefault(
     UInt(4.W),
     (Fill(4, instSizeByte) & "b0000".U(4.W))
@@ -359,7 +359,7 @@ class AXI4Bridge() extends Module with AXI4Config with InstConfig {
   protected val memSizeWord     = WireDefault(io.mem.size === AXI4Bridge.SIZE_W)
   protected val memSizeDouble   = WireDefault(io.mem.size === AXI4Bridge.SIZE_D)
 
-  protected val memAddrOpA = WireDefault(UInt(4.W), Cat(0.U, io.mem.addr(ALIGNED_WIDTH-1, 0)))
+  protected val memAddrOpA = WireDefault(UInt(4.W), Cat(0.U, io.mem.addr(ALIGNED_WIDTH - 1, 0)))
   protected val memAddrOpB = WireDefault(
     UInt(4.W),
     (Fill(4, memSizeByte) & "b0000".U(4.W))
@@ -399,8 +399,8 @@ class AXI4Bridge() extends Module with AXI4Config with InstConfig {
       | ((Fill(8, memSizeDouble) & "b1111_1111".U(8.W)))
   )
 
-  protected val memStrbLow = WireDefault(UInt((AxiDataWidth/8).W), memStrb << io.mem.addr(ALIGNED_WIDTH-1, 0))
-  protected val memStrbHig = WireDefault(UInt((AxiDataWidth/8).W), memStrb >> ((AxiDataWidth/8).U - io.mem.addr(ALIGNED_WIDTH-1, 0)))
+  protected val memStrbLow = WireDefault(UInt((AxiDataWidth / 8).W), memStrb << io.mem.addr(ALIGNED_WIDTH - 1, 0))
+  protected val memStrbHig = WireDefault(UInt((AxiDataWidth / 8).W), memStrb >> ((AxiDataWidth / 8).U - io.mem.addr(ALIGNED_WIDTH - 1, 0)))
 
   protected val memAxiUser  = Fill(AxiUserLen, "b0".U(1.W))
   protected val memReady    = RegInit(false.B)

rtl/tc_l2/src/main/scala/core/CSRReg.scala

@@ -8,9 +8,10 @@ import treecorel2.common.ConstVal._
 class CSRReg() extends Module with InstConfig {
   val io = IO(new Bundle {
     // from id
+    val inst:           INSTIO = new INSTIO
     val rdAddrIn:       UInt   = Input(UInt(CSRAddrLen.W))
     val instOperTypeIn: UInt   = Input(UInt(InstOperTypeLen.W))
-    val inst:           INSTIO = new INSTIO
+
     // from ex's out
     val wtEnaIn:  Bool = Input(Bool())
     val wtDataIn: UInt = Input(UInt(BusWidth.W))