aiger2: fix empty cell input

[widlarizer]

Fix #5169 in a boring way. Not sure how to test this, since the reproducer uses abc_new without arguments which will fail anyway. abc_new is never called by the test suite so I can't extend an existing test either

[Ravenslofty]

Not sure how to test this, since the reproducer uses abc_new without arguments which will fail anyway.

That's kind of odd to me, given that abc9 is a valid command by itself, and I was told that abc_new should behave similarly.

[widlarizer]

On a decent proc'd design like tests/sat/alu.v, abc9 will fail with ERROR: Design does not contain any modules with (* abc9_lut *).. abc9 -lut 4 is fine. abc_new will fail with an abort since it supplies no default script to abc9_exe. I could add abc_speed_gia_only.script from ORFS. However, I'd still get ERROR: Malformed design (2) if I ran abc_new -script abc_speed_gia_only.script -liberty ../../tests/liberty/normal.lib -liberty ../../tests/liberty/dff.lib

[widlarizer]

I forgot logger -expect error ... was a thing

[Ravenslofty]

On a decent proc'd design like tests/sat/alu.v, abc9 will fail with ERROR: Design does not contain any modules with (* abc9_lut *).

(Perhaps there's a miscommunication here?

yosys/techlibs/lattice/synth_lattice.cc

Line 545 in 9871e9b

run("abc9" + abc9_opts);

This is, to me, shows abc9 is a valid command by itself.)

[widlarizer]

I don't know what you mean sorry

[Ravenslofty]

read_verilog alu.v
read_verilog -lib -specify +/lattice/cells_sim_ecp5.v
proc
abc9

[widlarizer]

I see. Well, neither is a command you could run on an arbitrary well-formed design without more commands in the context, or added arguments. There's a test now though