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2.1.0

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@shtaxxx shtaxxx released this 04 Apr 13:49
2.1.0
0973afa

Update

  • Improved the DMA transfer performance of AXIM by supporting multiple in-flight transactions. DMA request FIFOs are introduced.
  • Introduced dma_read_packed and dma_write_packed for packed DMA transfers by MultibankRAM. The behavior is same as the dma_read and dma_write of MultibankRAM in the previous version, but the addressing mode is different.
  • Changed the addressing granularity of DMA transfers for MultibankRAM.
  • Implemented dma_read_bcast that broadcast a value to multiple RAMs.
  • Reimplemented the burst read/write methods of RAM without the obsoleted dataflow classes. Old dataflow related methods are removed.
  • AxiMemoryModel supports multiple in-flight transactions. Old AxiMemoryModel is renamed as AxiSerialMemoryModel.
  • Removed AXIM2.
  • Bug fix of multiple driver in stream.Substream.
  • Added some actual examples running on Ultra96V2 with generated RTL source codes and synthesized bitstreams.

This version is suitable for NNgen 1.3.3.

Test environment

macOS 12.3.1 (Apple Silicon M1 Max)

Python 3.9.5

  • Icarus Verilog 11.0
  • Pyverilog 1.3.0
  • numpy 1.22.1
  • Jinja2 3.0.3

Ubuntu 20.04.4 (AMD Ryzen 9 5950X)

Python 3.9.5

  • Icarus Verilog 10.3
  • Pyverilog 1.3.0
  • numpy 1.22.1
  • Jinja2 3.0.3

Python 3.7.7

  • Icarus Verilog 10.3
  • Pyverilog 1.3.0
  • numpy 1.21.5
  • Jinja2 3.0.3
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