Merge branch 'develop' into 2.1.0-rc

Author: shtaxxx

veriloggen/stream/stypes.py

@@ -3968,7 +3968,7 @@ def _implement(self, m, seq, svalid=None, senable=None):
 
         if self.child.ivalid is not None:
             ivalid_cond = _and_vars(svalid, senable)
-            seq(self.child.ivalid(vtypes.Int(1, 1)), cond=ivalid_cond)
+            self.child.fsm.seq(self.child.ivalid(vtypes.Int(1, 1)), cond=ivalid_cond)
 
         for data, (name, cond) in zip(arg_data, self.conds.items()):
             enable_cond = _and_vars(svalid, senable, cond)
@@ -3977,7 +3977,7 @@ def _implement(self, m, seq, svalid=None, senable=None):
 
         if self.strm.dump and self.child.dump:
             dump_cond = _and_vars(svalid, senable)
-            seq(self.child.dump_enable(self.strm.dump_enable), cond=dump_cond)
+            self.child.seq(self.child.dump_enable(self.strm.dump_enable), cond=dump_cond)
 
         self.sig_data = vtypes.Int(0)
 
@@ -4027,10 +4027,10 @@ def _implement(self, m, seq, svalid=None, senable=None):
             ii_count(0)
         )
 
-        seq.If(self.strm.busy, self.child.ivalid)(
+        self.child.fsm.seq.If(self.strm.busy, self.child.ivalid)(
             self.child.ivalid(vtypes.Int(0, 1))
         )
-        seq.If(enable_cond, ii_count == 0)(
+        self.child.fsm.seq.If(enable_cond, ii_count == 0)(
             self.child.ivalid(vtypes.Int(1, 1))
         )
 
@@ -4041,7 +4041,7 @@ def _implement(self, m, seq, svalid=None, senable=None):
 
         if self.strm.dump and self.child.dump:
             dump_cond = _and_vars(svalid, senable)
-            seq(self.child.dump_enable(self.strm.dump_enable), cond=dump_cond)
+            self.child.seq(self.child.dump_enable(self.strm.dump_enable), cond=dump_cond)
 
         self.sig_data = vtypes.Int(0)
 
@@ -5005,7 +5005,7 @@ def ReduceArgMin(right, size=None, interval=None, initval=0,
     _min = ReduceMin(right, size, interval, initval,
                      enable, reset, reg_initval, width, signed)
     counter = Counter(size, dependency=right, enable=enable, reset=reset)
-    update = NotEq(_min, reduce_min.prev(1))
+    update = NotEq(_min, _min.prev(1))
     update.latency = 0
     index = Predicate(counter, update)
     return index, _min

veriloggen/thread/stream.py

@@ -3838,7 +3838,7 @@ def _implement(self, m, seq, svalid=None, senable=None):
         cond_delay = self.reset_delay - 1
         child_source_busy = seq.Prev(self.strm.source_busy, cond_delay, cond=self.strm.oready)
         cond = _and_vars(senable, self.strm.busy)
-        seq(self.child.source_busy(child_source_busy), cond=cond)
+        self.child.fsm.seq(self.child.source_busy(child_source_busy), cond=cond)
 
         # parent to child
         util.add_disable_cond(self.child.is_root, self.strm.busy, 0)
@@ -3886,7 +3886,7 @@ def _implement(self, m, seq, svalid=None, senable=None):
         cond_delay = self.reset_delay - 1
         child_source_busy = seq.Prev(self.strm.source_busy, cond_delay, cond=self.strm.oready)
         cond = _and_vars(senable, self.strm.busy)
-        seq(self.child.source_busy(child_source_busy), cond=cond)
+        self.child.fsm.seq(self.child.source_busy(child_source_busy), cond=cond)
 
         # parent to child
         util.add_disable_cond(self.child.is_root, self.strm.busy, 0)