rx: Update rx gcc from Renesas release

gcc/common/config/rx/rx-common.cc

@@ -51,11 +51,11 @@ rx_handle_option (struct gcc_options *opts,
       return value >= 0 && value <= 4;
 
     case OPT_mcpu_:
-      if ((enum rx_cpu_types) value == RX200 || 
+      if ((enum rx_cpu_types) value == RX200 ||
           (enum rx_cpu_types) value == RX100)
 	opts->x_target_flags |= MASK_NO_USE_FPU;
       break;
-      
+
     case OPT_fpu:
       if (opts->x_rx_cpu_type == RX200)
 	error_at (loc, "the RX200 cpu does not have FPU hardware");

gcc/config.gcc

@@ -187,7 +187,7 @@
 #			the --with-sysroot configure option or the
 #			--sysroot command line option is used this
 #			will be relative to the sysroot.
-# target_type_format_char 
+# target_type_format_char
 # 			The default character to be used for formatting
 #			the attribute in a
 #			.type symbol_name, ${t_t_f_c}<property>
@@ -3254,6 +3254,8 @@ rx-*-elf*)
 	        tmake_file="${tmake_file} rx/t-rx"
 		;;
 	esac
+	c_target_objs="rx-pragma.o"
+	cxx_target_objs="rx-pragma.o"
 	extra_options="${extra_options} rx/elf.opt"
 	;;
 rx-*-linux*)

gcc/config/rx/constraints.md

@@ -32,6 +32,13 @@
   )
 )
 
+(define_constraint "Ibset"
+  "@internal An unsigned 8-bit immediate value with a single bit set"
+  (and (match_code "const_int")
+       (match_test "exact_log2 (ival) != -1")
+  )
+)
+
 (define_constraint "Sint08"
   "@internal A signed 8-bit immediate value"
   (and (match_code "const_int")
@@ -63,6 +70,20 @@
   )
 )
 
+(define_constraint "Uint05"
+  "@internal An unsigned 5-bit immediate value"
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (ival, 0, 31)")
+  )
+)
+
+(define_constraint "Uintz5"
+  "@internal An unsigned ,non-zero, 5-bit immediate value"
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (ival, 1, 31)")
+  )
+)
+
 (define_constraint "NEGint4"
   "@internal An signed 4-bit negative immediate value"
   (and (match_code "const_int")
@@ -87,6 +108,14 @@
   )
 )
 
+(define_register_constraint "DFPUreg" "DOUBLE_REGS"
+  "The DFPU registers")
+
+(define_constraint "DoubleC"
+  "Const double."
+  (match_code "const_double")
+)
+
 (define_constraint "Rpid"
   "A MEM to a PID variable"
   (and (match_code "mem")
@@ -107,6 +136,56 @@
   )
 )
 
+(define_memory_constraint "Rreg"
+  "A MEM which only uses REG addressing."
+  (and (match_code "mem")
+       (match_code "reg" "0")
+  )
+)
+
+(define_memory_constraint "Rd05"
+  "A MEM which only uses REG+INT addressing with 5-bit displacement."
+ (and (match_code "mem")
+       (and (match_code "plus" "0")
+           (and (match_code "reg,subreg" "00")
+                (and (match_code "const_int" "01")
+                     (match_test "IN_RANGE (INTVAL (XEXP (XEXP (op, 0), 1)),
+                                            0, 31 * GET_MODE_SIZE (GET_MODE (op)))")
+                )
+           )
+       )
+  )
+)
+
+(define_memory_constraint "Rd08"
+  "A MEM which only uses REG+INT addressing with 8-bit displacement."
+  (and (match_code "mem")
+       (and (match_code "plus" "0")
+           (and (match_code "reg,subreg" "00")
+                (and (match_code "const_int" "01")
+                     (match_test "IN_RANGE (INTVAL (XEXP (XEXP (op, 0), 1)),
+                                            0, 255 * GET_MODE_SIZE (GET_MODE (op)))")
+                )
+           )
+       )
+  )
+)
+
+(define_constraint "RXV2"
+"Reg constraint for RXV2 instructions"
+(and (match_code "reg")
+	(match_test "TARGET_RXV2")
+	)
+)
+
+(define_constraint "RXV3"
+"Reg constraint for RXV3 instructions"
+(and (match_code "reg")
+  (match_test "TARGET_RXV3")
+  )
+)
+
+
 (define_constraint "CALL_OP_SYMBOL_REF"
 "constraint for call instructions using symbol ref"
 (and (match_test "!TARGET_JSR")

gcc/config/rx/elf.opt

@@ -34,7 +34,7 @@ Generate assembler output that is compatible with the Renesas AS100 assembler.
 ;---------------------------------------------------
 
 mint-register=
-Target RejectNegative Joined UInteger Var(rx_interrupt_registers) Init(0)
+Target RejectNegative Joined UInteger Var(rx_deferred_options) Defer
 Specifies the number of registers to reserve for interrupt handlers.
 
 ;---------------------------------------------------

gcc/config/rx/predicates.md

@@ -49,6 +49,16 @@
        (match_test "IN_RANGE (INTVAL (op), 0, 31)"))
 )
 
+(define_predicate "rx_bitclr_operand"
+  (and (match_code "const_int")
+       (match_test "exact_log2 (~INTVAL (op)) != -1"))
+)
+
+(define_predicate "rx_bitset_operand"
+  (and (match_code "const_int")
+       (match_test "exact_log2 (INTVAL (op)) != -1"))
+)
+
 (define_predicate "rx_restricted_mem_operand"
   (and (match_code "mem")
        (match_test "rx_is_restricted_memory_address (XEXP (op, 0), mode)"))
@@ -64,6 +74,13 @@
        (match_operand 0 "rx_restricted_mem_operand"))
 )
 
+(define_predicate "rx_speed_source_operand"
+  (ior (match_operand 0 "register_operand")
+       (match_operand 0 "immediate_operand")
+       (and (match_test "optimize_size")
+            (match_operand 0 "rx_restricted_mem_operand")))
+)
+
 ;; Check that the operand is suitable as the source operand
 ;; for a comparison instruction.  This is the same as
 ;; rx_source_operand except that SUBREGs are allowed but
@@ -84,6 +101,18 @@
        (match_operand 0 "rx_restricted_mem_operand"))
 )
 
+(define_predicate "rx_speed_minmaxex_operand"
+  (ior (match_operand 0 "immediate_operand")
+       (and (match_test "optimize_size")
+            (match_operand 0 "rx_restricted_mem_operand")))
+)
+
+(define_predicate "rx_speed_compare_operand"
+  (ior (match_operand 0 "register_operand")
+       (and (match_test "optimize_size")
+            (match_operand 0 "rx_restricted_mem_operand")))
+)
+
 ;; Return true if OP is a store multiple operation.  This looks like:
 ;;
 ;;   [(set (SP) (MINUS (SP) (INT)))
@@ -114,33 +143,15 @@
       || ! CONST_INT_P (XEXP (SET_SRC (element), 1)))
     return false;
 
-  /* Check that the next element is the first push.  */
-  element = XVECEXP (op, 0, 1);
-  if (   ! SET_P (element)
-      || ! REG_P (SET_SRC (element))
-      || GET_MODE (SET_SRC (element)) != SImode
-      || ! MEM_P (SET_DEST (element))
-      || GET_MODE (SET_DEST (element)) != SImode
-      || GET_CODE (XEXP (SET_DEST (element), 0)) != MINUS
-      || ! REG_P (XEXP (XEXP (SET_DEST (element), 0), 0))
-      ||   REGNO (XEXP (XEXP (SET_DEST (element), 0), 0)) != SP_REG
-      || ! CONST_INT_P (XEXP (XEXP (SET_DEST (element), 0), 1))
-      || INTVAL (XEXP (XEXP (SET_DEST (element), 0), 1))
-        != GET_MODE_SIZE (SImode))
-    return false;
-
-  src_regno = REGNO (SET_SRC (element));
-
   /* Check that the remaining elements use SP-<disp>
      addressing and decreasing register numbers.  */
-  for (i = 2; i < count; i++)
+    for (i = 1; i < count - 1; i++)	
     {
       element = XVECEXP (op, 0, i);
 
       if (   ! SET_P (element)
 	  || ! REG_P (SET_SRC (element))
 	  || GET_MODE (SET_SRC (element)) != SImode
-	  || REGNO (SET_SRC (element)) != src_regno - (i - 1)
 	  || ! MEM_P (SET_DEST (element))
 	  || GET_MODE (SET_DEST (element)) != SImode
 	  || GET_CODE (XEXP (SET_DEST (element), 0)) != MINUS

gcc/config/rx/rx-opts.h

@@ -22,10 +22,38 @@
 
 enum rx_cpu_types
 {
+  RX13T,
+  RX230,
+  RX71M,
+  RX72T,
+  RX64M,
   RX600,
   RX610,
+  RX66T,
   RX200,
-  RX100
+  RX100,
+  RX140,
+  RX_CPUUNINIT
+};
+enum rx_tfu_versions
+{
+  RX_TFUV1,
+  RX_TFUV2,
+  RX_TFUVUNINIT
+};
+enum rx_isa_versions
+{
+  RX_ISAV1,
+  RX_ISAV2,
+  RX_ISAV3,
+  RX_ISAUNINIT
+};
+
+enum rx_tfu_types
+{
+  RX_INTRINSIC,
+  RX_MATHLIB,
+  RX_TFUUNINIT
 };
 
 #endif

gcc/config/rx/rx-pragma.c

@@ -0,0 +1,56 @@
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "tree.h"
+#include "c-family/c-pragma.h"
+#include "c-family/c-common.h"
+#include "diagnostic-core.h"
+#include "cpplib.h"
+#include "hard-reg-set.h"
+#include "output.h"
+#include "rx-protos.h"
+#include "function.h"
+#define MAX_RECOG_OPERANDS 10
+#include "reload.h"
+#include "target.h"
+
+/* Implements the "pragma ADDRESS" pragma.  This pragma takes a
+ *    variable name and an address, and arranges for that variable to be
+ *       "at" that address.  The variable is also made volatile.  */
+static void
+rx_pragma_address (cpp_reader * reader ATTRIBUTE_UNUSED)
+{
+  /* on off */
+  tree var, addr;
+  enum cpp_ttype type;
+
+  type = pragma_lex (&var);
+  if (type == CPP_NAME)
+    {
+      type = pragma_lex (&addr);
+      if (type == CPP_NUMBER)
+	{
+	  if (var != error_mark_node)
+	    {
+	      unsigned uaddr = tree_to_uhwi (addr);
+	      rx_note_pragma_address (IDENTIFIER_POINTER (var), uaddr);
+	    }
+
+	  type = pragma_lex (&var);
+	  if (type != CPP_EOF)
+	    {
+	      error ("junk at end of #pragma ADDRESS");
+	    }
+	  return;
+	}
+    }
+  error ("malformed #pragma ADDRESS variable address");
+}
+
+void
+rx_register_pragmas (void)
+{
+  c_register_pragma (NULL, "ADDRESS", rx_pragma_address);
+  c_register_pragma (NULL, "address", rx_pragma_address);
+}

gcc/config/rx/rx-protos.h

@@ -25,6 +25,14 @@ extern bool             rx_can_use_simple_return (void);
 extern void		rx_expand_epilogue (bool);
 extern void		rx_expand_prologue (void);
 extern int		rx_initial_elimination_offset (int, int);
+extern void		rx_register_pragmas (void);
+extern void 		rx_note_pragma_address (const char *varname, unsigned address);
+extern void		rx_output_aligned_common (FILE *stream, tree decl ATTRIBUTE_UNUSED, const char *name,int size, int align);
+extern void             rx_adjust_reg_alloc_order (void);
+extern enum reg_class  rx_regno_class (int);
+extern bool  rx_hard_regno_mode_ok (unsigned regno, machine_mode mode);
+extern unsigned int  rx_regmode_natural_size (enum machine_mode mode);
+extern unsigned int rx_dbx_register_number (unsigned int);
 
 bool is_interrupt_func (const_tree decl);
 bool is_fast_interrupt_func (const_tree decl);
@@ -53,6 +61,7 @@ extern int		rx_adjust_insn_length (rtx_insn *, int);
 extern align_flags	rx_align_for_label (rtx_insn *, int);
 extern void             rx_emit_stack_popm (rtx *, bool);
 extern void             rx_emit_stack_pushm (rtx *);
+extern void             rx_emit_stack_dpushm (rtx *);
 extern char *		rx_gen_move_template (rtx *, bool);
 extern bool		rx_is_legitimate_constant (machine_mode, rtx);
 extern bool		rx_is_restricted_memory_address (rtx,