Add support for Zbc carry-less multiplication extension

Add support for the RISC-V Zbc carry-less multiplication extension.
This extension introduces instructions for carry-less multiplication,
enabling efficient operations in cryptographic algorithms,
error-correcting codes, and other specialized applications.

Supporting the Zbc extension improves compatibility with the RISC-V
specification and enables optimized handling of carry-less
multiplication tasks.

Author: visitorckw

Makefile

@@ -115,6 +115,10 @@ $(call set-feature, Zba)
 ENABLE_Zbb ?= 1
 $(call set-feature, Zbb)
 
+# Zbc Carry-less multiplication
+ENABLE_Zbc ?= 1
+$(call set-feature, Zbc)
+
 ENABLE_FULL4G ?= 0
 
 # Experimental SDL oriented system calls

src/decode.c

@@ -725,7 +725,7 @@ static inline bool op_op(rv_insn_t *ir, const uint32_t insn)
         break;
 #endif /* RV32_HAS(Zba) */
 
-#if RV32_HAS(Zbb)
+#if RV32_HAS(Zbb) || RV32_HAS(Zbc)
     /* inst   funct7  rs2 rs1 funct3 rd opcode
      * ------+-------+---+---+------+--+-------
      * MAX    0000101 rs2 rs1 110    rd 0110011
@@ -737,6 +737,7 @@ static inline bool op_op(rv_insn_t *ir, const uint32_t insn)
      */
     case 0b0000101:
         switch (funct3) {
+#if RV32_HAS(Zbb)
         case 0b110: /* max */
             ir->opcode = rv_insn_max;
             break;
@@ -749,10 +750,24 @@ static inline bool op_op(rv_insn_t *ir, const uint32_t insn)
         case 0b101: /* minu */
             ir->opcode = rv_insn_minu;
             break;
+#endif
+#if RV32_HAS(Zbc)
+        case 0b001: /*clmul */
+            ir->opcode = rv_insn_clmul;
+            break;
+        case 0b011: /*clmulh */
+            ir->opcode = rv_insn_clmulh;
+            break;
+        case 0b010: /*clmulr */
+            ir->opcode = rv_insn_clmulr;
+            break;
+#endif
         default: /* illegal instruction */
             return false;
         }
         break;
+#endif
+#if RV32_HAS(Zbb)
     case 0b0110000:
         switch (funct3) {
         case 0b001: /* rol */

src/decode.h

@@ -123,6 +123,12 @@ enum op_field {
         _(rori, 0, 4, 0, ENC(rs1, rd))                 \
         _(orcb, 0, 4, 0, ENC(rs1, rd))                 \
         _(rev8, 0, 4, 0, ENC(rs1, rd))                 \
+    )                                                  \
+     /* RV32 Zbc Standard Extension */                 \
+    IIF(RV32_HAS(Zbc))(                                \
+        _(clmul, 0, 4, 0, ENC(rs1, rs2, rd))           \
+        _(clmulh, 0, 4, 0, ENC(rs1, rs2, rd))          \
+        _(clmulr, 0, 4, 0, ENC(rs1, rs2, rd))          \
     )                                                  \
     /* RV32M Standard Extension */                     \
     IIF(RV32_HAS(EXT_M))(                              \

src/feature.h

@@ -47,6 +47,11 @@
 #define RV32_FEATURE_Zbb 1
 #endif
 
+/* Zbc Carry-less multiplication */
+#ifndef RV32_FEATURE_Zbc
+#define RV32_FEATURE_Zbc 1
+#endif
+
 /* Experimental SDL oriented system calls */
 #ifndef RV32_FEATURE_SDL
 #define RV32_FEATURE_SDL 1

src/rv32_constopt.c

@@ -1169,3 +1169,23 @@ CONSTOPT(rev8, {
         info->is_constant[ir->rd] = false;
 })
 #endif
+
+#if RV32_HAS(Zbc)
+/* CLMUL */
+CONSTOPT(clmul, {
+    if (ir->rd)
+        info->is_constant[ir->rd] = false;
+})
+
+/* CLMULH */
+CONSTOPT(clmulh, {
+    if (ir->rd)
+        info->is_constant[ir->rd] = false;
+})
+
+/* CLMULR */
+CONSTOPT(clmulr, {
+    if (ir->rd)
+        info->is_constant[ir->rd] = false;
+})
+#endif

src/rv32_template.c

@@ -2837,3 +2837,51 @@ RVOP(
     }))
 
 #endif
+
+/* RV32Zbc Standard Extension */
+
+#if RV32_HAS(Zbc)
+
+/* CLMUL */
+RVOP(
+    clmul,
+    {
+        uint32_t output = 0;
+        for (int i = 0; i < 32; i++)
+            if ((rv->X[ir->rs2] >> i) & 1)
+                output ^= rv->X[ir->rs1] << i;
+        rv->X[ir->rd] = output;
+    },
+    GEN({
+        assert; /* FIXME: Implement */
+    }))
+
+/* CLMULH */
+RVOP(
+    clmulh,
+    {
+        uint32_t output = 0;
+        for (int i = 1; i < 32; i++)
+            if ((rv->X[ir->rs2] >> i) & 1)
+                output ^= rv->X[ir->rs1] >> (32 - i);
+        rv->X[ir->rd] = output;
+    },
+    GEN({
+        assert; /* FIXME: Implement */
+    }))
+
+/* CLMULR */
+RVOP(
+    clmulr,
+    {
+        uint32_t output = 0;
+        for (int i = 0; i < 32; i++)
+            if ((rv->X[ir->rs2] >> i) & 1)
+                output ^= rv->X[ir->rs1] >> (32 - i - 1);
+        rv->X[ir->rd] = output;
+    },
+    GEN({
+        assert; /* FIXME: Implement */
+    }))
+
+#endif

src/t2c_template.c

@@ -839,6 +839,14 @@ T2C_OP(orcb, { __UNREACHABLE; })
 T2C_OP(rev8, { __UNREACHABLE; })
 #endif
 
+#if RV32_HAS(Zbc)
+T2C_OP(clmul, { __UNREACHABLE; })
+
+T2C_OP(clmulh, { __UNREACHABLE; })
+
+T2C_OP(clmulr, { __UNREACHABLE; })
+#endif
+
 T2C_OP(fuse1, {
     opcode_fuse_t *fuse = ir->fuse;
     for (int i = 0; i < ir->imm2; i++) {