Add support for Zbb basic bit-manipulation extension

Add support for the RISC-V Zbb basic bit-manipulation extension. This
extension introduces fundamental bitwise operations such as bit
counting, bit field extraction, and bit rotation, enabling efficient
data manipulation and low-level computation.

Supporting the Zbb extension improves compatibility with the RISC-V
specification and enables optimized handling of bitwise operations in a
wide range of applications.

Author: visitorckw

Makefile

@@ -111,6 +111,10 @@ $(call set-feature, Zifencei)
 ENABLE_Zba ?= 1
 $(call set-feature, Zba)
 
+# Zbb Basic bit-manipulation
+ENABLE_Zbb ?= 1
+$(call set-feature, Zbb)
+
 ENABLE_FULL4G ?= 0
 
 # Experimental SDL oriented system calls

src/decode.c

@@ -464,6 +464,28 @@ static inline bool op_op_imm(rv_insn_t *ir, const uint32_t insn)
         ir->opcode = rv_insn_addi;
         break;
     case 1: /* SLLI: Shift Left Logical */
+#if RV32_HAS(Zbb)
+        if (ir->imm == 0b011000000000) { /* clz */
+            ir->opcode = rv_insn_clz;
+            return true;
+        }
+        if (ir->imm == 0b011000000001) { /* ctz */
+            ir->opcode = rv_insn_ctz;
+            return true;
+        }
+        if (ir->imm == 0b011000000010) { /* cpop */
+            ir->opcode = rv_insn_cpop;
+            return true;
+        }
+        if (ir->imm == 0b011000000100) { /* sext.b */
+            ir->opcode = rv_insn_sextb;
+            return true;
+        }
+        if (ir->imm == 0b011000000101) { /* sext.h */
+            ir->opcode = rv_insn_sexth;
+            return true;
+        }
+#endif
         ir->opcode = rv_insn_slli;
         if (unlikely(ir->imm & (1 << 5)))
             return false;
@@ -478,6 +500,20 @@ static inline bool op_op_imm(rv_insn_t *ir, const uint32_t insn)
         ir->opcode = rv_insn_xori;
         break;
     case 5:
+#if RV32_HAS(Zbb)
+        if (ir->imm >> 5 == 0b0110000) { /* rori */
+            ir->opcode = rv_insn_rori;
+            return true;
+        }
+        if (ir->imm == 0b001010000111) { /* orc.b */
+            ir->opcode = rv_insn_orcb;
+            return true;
+        }
+        if (ir->imm == 0b011010011000) { /* rev8 */
+            ir->opcode = rv_insn_rev8;
+            return true;
+        }
+#endif
         /* SLL, SRL, and SRA perform logical left, logical right, and
          * arithmetic right shifts on the value in register rs1.
          */
@@ -689,6 +725,53 @@ static inline bool op_op(rv_insn_t *ir, const uint32_t insn)
         break;
 #endif /* RV32_HAS(Zba) */
 
+#if RV32_HAS(Zbb)
+    /* inst   funct7  rs2 rs1 funct3 rd opcode
+     * ------+-------+---+---+------+--+-------
+     * MAX    0000101 rs2 rs1 110    rd 0110011
+     * MIN    0000101 rs2 rs1 100    rd 0110011
+     * MAXU   0000101 rs2 rs1 111    rd 0110011
+     * MINU   0000101 rs2 rs1 101    rd 0110011
+     * ROL    0110000 rs2 rs1 001    rd 0110011
+     * ROR    0110000 rs2 rs1 101    rd 0110011
+     */
+    case 0b0000101:
+        switch (funct3) {
+        case 0b110: /* max */
+            ir->opcode = rv_insn_max;
+            break;
+        case 0b100: /* min */
+            ir->opcode = rv_insn_min;
+            break;
+        case 0b111: /* maxu */
+            ir->opcode = rv_insn_maxu;
+            break;
+        case 0b101: /* minu */
+            ir->opcode = rv_insn_minu;
+            break;
+        default: /* illegal instruction */
+            return false;
+        }
+        break;
+    case 0b0110000:
+        switch (funct3) {
+        case 0b001: /* rol */
+            ir->opcode = rv_insn_rol;
+            break;
+        case 0b101: /* ror */
+            ir->opcode = rv_insn_ror;
+            break;
+        default: /* illegal instruction */
+            return false;
+        }
+        break;
+    case 0b0000100:
+        if (unlikely(ir->rs2))
+            return false;
+        ir->opcode = rv_insn_zexth;
+        break;
+#endif /* RV32_HAS(Zbb) */
+
     case 0b0100000:
         switch (funct3) {
         case 0b000: /* SUB: Substract */
@@ -697,6 +780,18 @@ static inline bool op_op(rv_insn_t *ir, const uint32_t insn)
         case 0b101: /* SRA: Shift Right Arithmetic */
             ir->opcode = rv_insn_sra;
             break;
+#if RV32_HAS(Zbb)
+        case 0b111: /* ANDN */
+            ir->opcode = rv_insn_andn;
+            break;
+        case 0b110: /* ORN */
+            ir->opcode = rv_insn_orn;
+            break;
+        case 0b100: /* XNOR */
+            ir->opcode = rv_insn_xnor;
+            break;
+#endif /* RV32_HAS(Zbb) */
+
         default: /* illegal instruction */
             return false;
         }

src/decode.h

@@ -103,6 +103,27 @@ enum op_field {
         _(sh2add, 0, 4, 0, ENC(rs1, rs2, rd))          \
         _(sh3add, 0, 4, 0, ENC(rs1, rs2, rd))          \
     )                                                  \
+    /* RV32 Zbb Standard Extension */                  \
+    IIF(RV32_HAS(Zbb))(                                \
+        _(andn, 0, 4, 0, ENC(rs1, rs2, rd))            \
+        _(orn, 0, 4, 0, ENC(rs1, rs2, rd))             \
+        _(xnor, 0, 4, 0, ENC(rs1, rs2, rd))            \
+        _(clz, 0, 4, 0, ENC(rs1, rd))                  \
+        _(ctz, 0, 4, 0, ENC(rs1, rd))                  \
+        _(cpop, 0, 4, 0, ENC(rs1, rd))                 \
+        _(max, 0, 4, 0, ENC(rs1, rs2, rd))             \
+        _(maxu, 0, 4, 0, ENC(rs1, rs2, rd))            \
+        _(min, 0, 4, 0, ENC(rs1, rs2, rd))             \
+        _(minu, 0, 4, 0, ENC(rs1, rs2, rd))            \
+        _(sextb, 0, 4, 0, ENC(rs1, rd))                \
+        _(sexth, 0, 4, 0, ENC(rs1, rd))                \
+        _(zexth, 0, 4, 0, ENC(rs1, rd))                \
+        _(rol, 0, 4, 0, ENC(rs1, rs2, rd))             \
+        _(ror, 0, 4, 0, ENC(rs1, rs2, rd))             \
+        _(rori, 0, 4, 0, ENC(rs1, rd))                 \
+        _(orcb, 0, 4, 0, ENC(rs1, rd))                 \
+        _(rev8, 0, 4, 0, ENC(rs1, rd))                 \
+    )                                                  \
     /* RV32M Standard Extension */                     \
     IIF(RV32_HAS(EXT_M))(                              \
         _(mul, 0, 4, 1, ENC(rs1, rs2, rd))             \

src/feature.h

@@ -42,6 +42,11 @@
 #define RV32_FEATURE_Zba 1
 #endif
 
+/* Zbb Basic bit-manipulation */
+#ifndef RV32_FEATURE_Zbb
+#define RV32_FEATURE_Zbb 1
+#endif
+
 /* Experimental SDL oriented system calls */
 #ifndef RV32_FEATURE_SDL
 #define RV32_FEATURE_SDL 1

src/rv32_constopt.c

@@ -1059,3 +1059,113 @@ CONSTOPT(sh3add, {
         info->is_constant[ir->rd] = false;
 })
 #endif
+
+#if RV32_HAS(Zbb)
+/* ANDN */
+CONSTOPT(andn, {
+    if (ir->rd)
+        info->is_constant[ir->rd] = false;
+})
+
+/* ORN */
+CONSTOPT(orn, {
+    if (ir->rd)
+        info->is_constant[ir->rd] = false;
+})
+
+/* XNOR */
+CONSTOPT(xnor, {
+    if (ir->rd)
+        info->is_constant[ir->rd] = false;
+})
+
+/* CLZ */
+CONSTOPT(clz, {
+    if (ir->rd)
+        info->is_constant[ir->rd] = false;
+})
+
+/* CTZ */
+CONSTOPT(ctz, {
+    if (ir->rd)
+        info->is_constant[ir->rd] = false;
+})
+
+/* CPOP */
+CONSTOPT(cpop, {
+    if (ir->rd)
+        info->is_constant[ir->rd] = false;
+})
+
+/* MAX */
+CONSTOPT(max, {
+    if (ir->rd)
+        info->is_constant[ir->rd] = false;
+})
+
+/* MAXU */
+CONSTOPT(maxu, {
+    if (ir->rd)
+        info->is_constant[ir->rd] = false;
+})
+
+/* MIN */
+CONSTOPT(min, {
+    if (ir->rd)
+        info->is_constant[ir->rd] = false;
+})
+
+/* MINU */
+CONSTOPT(minu, {
+    if (ir->rd)
+        info->is_constant[ir->rd] = false;
+})
+
+/* SEXT.B */
+CONSTOPT(sextb, {
+    if (ir->rd)
+        info->is_constant[ir->rd] = false;
+})
+
+/* SEXT.H */
+CONSTOPT(sexth, {
+    if (ir->rd)
+        info->is_constant[ir->rd] = false;
+})
+
+/* ZEXT.H */
+CONSTOPT(zexth, {
+    if (ir->rd)
+        info->is_constant[ir->rd] = false;
+})
+
+/* ROL */
+CONSTOPT(rol, {
+    if (ir->rd)
+        info->is_constant[ir->rd] = false;
+})
+
+/* ROR */
+CONSTOPT(ror, {
+    if (ir->rd)
+        info->is_constant[ir->rd] = false;
+})
+
+/* RORI */
+CONSTOPT(rori, {
+    if (ir->rd)
+        info->is_constant[ir->rd] = false;
+})
+
+/* ORCB */
+CONSTOPT(orcb, {
+    if (ir->rd)
+        info->is_constant[ir->rd] = false;
+})
+
+/* REV8 */
+CONSTOPT(rev8, {
+    if (ir->rd)
+        info->is_constant[ir->rd] = false;
+})
+#endif