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system(L0): update STM32L0xx CMSIS Drivers to v1.9.3
Included in STM32CubeL0 FW v1.12.2 Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
1 parent d7020ae commit ba07738

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48 files changed

+2207
-659
lines changed

‎system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x4.h‎

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -14,13 +14,12 @@
1414
******************************************************************************
1515
* @attention
1616
*
17-
* <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
18-
* All rights reserved.</center></h2>
17+
* Copyright (c) 2016 STMicroelectronics.
18+
* All rights reserved.
1919
*
20-
* This software component is licensed by ST under BSD 3-Clause license,
21-
* the "License"; You may not use this file except in compliance with the
22-
* License. You may obtain a copy of the License at:
23-
* opensource.org/licenses/BSD-3-Clause
20+
* This software is licensed under terms that can be found in the LICENSE file
21+
* in the root directory of this software component.
22+
* If no LICENSE file comes with this software, it is provided AS-IS.
2423
*
2524
******************************************************************************
2625
*/
@@ -72,7 +71,7 @@ typedef enum
7271
/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
7372
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
7473
HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
75-
SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
74+
SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
7675
PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
7776
SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
7877

@@ -3614,7 +3613,7 @@ typedef struct
36143613
#define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */
36153614
#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
36163615

3617-
/*!< RTC congiguration */
3616+
/*!< RTC configuration */
36183617
#define RCC_CSR_RTCSEL_Pos (16U)
36193618
#define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
36203619
#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
@@ -5693,7 +5692,7 @@ typedef struct
56935692
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
56945693
((INSTANCE) == TIM21))
56955694

5696-
/***************** TIM Instances : external trigger input availabe ************/
5695+
/***************** TIM Instances : external trigger input available ************/
56975696
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
56985697
((INSTANCE) == TIM21))
56995698

@@ -5778,6 +5777,7 @@ typedef struct
57785777
#define RCC_CRS_IRQn RCC_IRQn
57795778
#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
57805779
#define ADC1_COMP_IRQn ADC1_IRQn
5780+
#define SVC_IRQn SVCall_IRQn
57815781

57825782
/* Aliases for __IRQHandler */
57835783
#define RNG_LPUART1_IRQHandler LPUART1_IRQHandler
@@ -5803,4 +5803,3 @@ typedef struct
58035803

58045804

58055805

5806-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

‎system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x6.h‎

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -14,13 +14,12 @@
1414
******************************************************************************
1515
* @attention
1616
*
17-
* <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
18-
* All rights reserved.</center></h2>
17+
* Copyright (c) 2016 STMicroelectronics.
18+
* All rights reserved.
1919
*
20-
* This software component is licensed by ST under BSD 3-Clause license,
21-
* the "License"; You may not use this file except in compliance with the
22-
* License. You may obtain a copy of the License at:
23-
* opensource.org/licenses/BSD-3-Clause
20+
* This software is licensed under terms that can be found in the LICENSE file
21+
* in the root directory of this software component.
22+
* If no LICENSE file comes with this software, it is provided AS-IS.
2423
*
2524
******************************************************************************
2625
*/
@@ -72,7 +71,7 @@ typedef enum
7271
/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
7372
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
7473
HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
75-
SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
74+
SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
7675
PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
7776
SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
7877

@@ -3647,7 +3646,7 @@ typedef struct
36473646
#define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */
36483647
#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
36493648

3650-
/*!< RTC congiguration */
3649+
/*!< RTC configuration */
36513650
#define RCC_CSR_RTCSEL_Pos (16U)
36523651
#define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
36533652
#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
@@ -5749,7 +5748,7 @@ typedef struct
57495748
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
57505749
((INSTANCE) == TIM21))
57515750

5752-
/***************** TIM Instances : external trigger input availabe ************/
5751+
/***************** TIM Instances : external trigger input available ************/
57535752
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
57545753
((INSTANCE) == TIM21))
57555754

@@ -5834,6 +5833,7 @@ typedef struct
58345833
#define RCC_CRS_IRQn RCC_IRQn
58355834
#define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
58365835
#define ADC1_COMP_IRQn ADC1_IRQn
5836+
#define SVC_IRQn SVCall_IRQn
58375837

58385838
/* Aliases for __IRQHandler */
58395839
#define RNG_LPUART1_IRQHandler LPUART1_IRQHandler
@@ -5859,4 +5859,3 @@ typedef struct
58595859

58605860

58615861

5862-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

‎system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x8.h‎

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -14,13 +14,12 @@
1414
******************************************************************************
1515
* @attention
1616
*
17-
* <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
18-
* All rights reserved.</center></h2>
17+
* Copyright (c) 2016 STMicroelectronics.
18+
* All rights reserved.
1919
*
20-
* This software component is licensed by ST under BSD 3-Clause license,
21-
* the "License"; You may not use this file except in compliance with the
22-
* License. You may obtain a copy of the License at:
23-
* opensource.org/licenses/BSD-3-Clause
20+
* This software is licensed under terms that can be found in the LICENSE file
21+
* in the root directory of this software component.
22+
* If no LICENSE file comes with this software, it is provided AS-IS.
2423
*
2524
******************************************************************************
2625
*/
@@ -72,7 +71,7 @@ typedef enum
7271
/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
7372
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
7473
HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
75-
SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
74+
SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
7675
PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
7776
SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
7877

@@ -3658,7 +3657,7 @@ typedef struct
36583657
#define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */
36593658
#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
36603659

3661-
/*!< RTC congiguration */
3660+
/*!< RTC configuration */
36623661
#define RCC_CSR_RTCSEL_Pos (16U)
36633662
#define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
36643663
#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
@@ -5744,7 +5743,7 @@ typedef struct
57445743
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
57455744
((INSTANCE) == TIM21))
57465745

5747-
/***************** TIM Instances : external trigger input availabe ************/
5746+
/***************** TIM Instances : external trigger input available ************/
57485747
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
57495748
((INSTANCE) == TIM21))
57505749

@@ -5830,6 +5829,7 @@ typedef struct
58305829
#define RCC_CRS_IRQn RCC_IRQn
58315830
#define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
58325831
#define ADC1_COMP_IRQn ADC1_IRQn
5832+
#define SVC_IRQn SVCall_IRQn
58335833

58345834
/* Aliases for __IRQHandler */
58355835
#define RNG_LPUART1_IRQHandler LPUART1_IRQHandler
@@ -5855,4 +5855,3 @@ typedef struct
58555855

58565856

58575857

5858-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

‎system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010xb.h‎

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -14,13 +14,12 @@
1414
******************************************************************************
1515
* @attention
1616
*
17-
* <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
18-
* All rights reserved.</center></h2>
17+
* Copyright (c) 2016 STMicroelectronics.
18+
* All rights reserved.
1919
*
20-
* This software component is licensed by ST under BSD 3-Clause license,
21-
* the "License"; You may not use this file except in compliance with the
22-
* License. You may obtain a copy of the License at:
23-
* opensource.org/licenses/BSD-3-Clause
20+
* This software is licensed under terms that can be found in the LICENSE file
21+
* in the root directory of this software component.
22+
* If no LICENSE file comes with this software, it is provided AS-IS.
2423
*
2524
******************************************************************************
2625
*/
@@ -72,7 +71,7 @@ typedef enum
7271
/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
7372
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
7473
HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
75-
SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
74+
SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
7675
PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
7776
SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
7877

@@ -3687,7 +3686,7 @@ typedef struct
36873686
#define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */
36883687
#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
36893688

3690-
/*!< RTC congiguration */
3689+
/*!< RTC configuration */
36913690
#define RCC_CSR_RTCSEL_Pos (16U)
36923691
#define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
36933692
#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
@@ -5816,7 +5815,7 @@ typedef struct
58165815
((INSTANCE) == TIM21) || \
58175816
((INSTANCE) == TIM22))
58185817

5819-
/***************** TIM Instances : external trigger input availabe ************/
5818+
/***************** TIM Instances : external trigger input available ************/
58205819
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
58215820
((INSTANCE) == TIM21) || \
58225821
((INSTANCE) == TIM22))
@@ -5906,6 +5905,7 @@ typedef struct
59065905
#define RCC_CRS_IRQn RCC_IRQn
59075906
#define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
59085907
#define ADC1_COMP_IRQn ADC1_IRQn
5908+
#define SVC_IRQn SVCall_IRQn
59095909

59105910
/* Aliases for __IRQHandler */
59115911
#define RNG_LPUART1_IRQHandler LPUART1_IRQHandler
@@ -5931,4 +5931,3 @@ typedef struct
59315931

59325932

59335933

5934-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

‎system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h‎

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -14,13 +14,12 @@
1414
******************************************************************************
1515
* @attention
1616
*
17-
* <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
18-
* All rights reserved.</center></h2>
17+
* Copyright (c) 2016 STMicroelectronics.
18+
* All rights reserved.
1919
*
20-
* This software component is licensed by ST under BSD 3-Clause license,
21-
* the "License"; You may not use this file except in compliance with the
22-
* License. You may obtain a copy of the License at:
23-
* opensource.org/licenses/BSD-3-Clause
20+
* This software is licensed under terms that can be found in the LICENSE file
21+
* in the root directory of this software component.
22+
* If no LICENSE file comes with this software, it is provided AS-IS.
2423
*
2524
******************************************************************************
2625
*/
@@ -72,7 +71,7 @@ typedef enum
7271
/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
7372
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
7473
HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
75-
SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
74+
SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
7675
PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
7776
SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
7877

@@ -3723,7 +3722,7 @@ typedef struct
37233722
#define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */
37243723
#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
37253724

3726-
/*!< RTC congiguration */
3725+
/*!< RTC configuration */
37273726
#define RCC_CSR_RTCSEL_Pos (16U)
37283727
#define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
37293728
#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
@@ -5835,7 +5834,7 @@ typedef struct
58355834
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
58365835
((INSTANCE) == TIM21))
58375836

5838-
/***************** TIM Instances : external trigger input availabe ************/
5837+
/***************** TIM Instances : external trigger input available ************/
58395838
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
58405839
((INSTANCE) == TIM21))
58415840

@@ -5920,6 +5919,7 @@ typedef struct
59205919
#define RCC_CRS_IRQn RCC_IRQn
59215920
#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
59225921
#define ADC1_IRQn ADC1_COMP_IRQn
5922+
#define SVC_IRQn SVCall_IRQn
59235923

59245924
/* Aliases for __IRQHandler */
59255925
#define RNG_LPUART1_IRQHandler LPUART1_IRQHandler
@@ -5945,4 +5945,3 @@ typedef struct
59455945

59465946

59475947

5948-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

‎system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l021xx.h‎

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -14,13 +14,12 @@
1414
******************************************************************************
1515
* @attention
1616
*
17-
* <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
18-
* All rights reserved.</center></h2>
17+
* Copyright (c) 2016 STMicroelectronics.
18+
* All rights reserved.
1919
*
20-
* This software component is licensed by ST under BSD 3-Clause license,
21-
* the "License"; You may not use this file except in compliance with the
22-
* License. You may obtain a copy of the License at:
23-
* opensource.org/licenses/BSD-3-Clause
20+
* This software is licensed under terms that can be found in the LICENSE file
21+
* in the root directory of this software component.
22+
* If no LICENSE file comes with this software, it is provided AS-IS.
2423
*
2524
******************************************************************************
2625
*/
@@ -72,7 +71,7 @@ typedef enum
7271
/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
7372
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
7473
HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
75-
SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
74+
SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
7675
PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
7776
SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
7877

@@ -3860,7 +3859,7 @@ typedef struct
38603859
#define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */
38613860
#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
38623861

3863-
/*!< RTC congiguration */
3862+
/*!< RTC configuration */
38643863
#define RCC_CSR_RTCSEL_Pos (16U)
38653864
#define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
38663865
#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
@@ -5975,7 +5974,7 @@ typedef struct
59755974
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
59765975
((INSTANCE) == TIM21))
59775976

5978-
/***************** TIM Instances : external trigger input availabe ************/
5977+
/***************** TIM Instances : external trigger input available ************/
59795978
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
59805979
((INSTANCE) == TIM21))
59815980

@@ -6060,6 +6059,7 @@ typedef struct
60606059
#define RCC_CRS_IRQn RCC_IRQn
60616060
#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
60626061
#define ADC1_IRQn ADC1_COMP_IRQn
6062+
#define SVC_IRQn SVCall_IRQn
60636063

60646064
/* Aliases for __IRQHandler */
60656065
#define LPUART1_IRQHandler AES_LPUART1_IRQHandler
@@ -6085,4 +6085,3 @@ typedef struct
60856085

60866086

60876087

6088-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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