Skip to content

Commit d0f4500

Browse files
therealproftherealprof
authored
Merge pull request #53 from HarkonenBade/adc-updates
Update the ADC code to take advantage of the named variants in stm32-rs v0.6.0
2 parents 1524cb1 + e081e82 commit d0f4500

File tree

2 files changed

+79
-61
lines changed

2 files changed

+79
-61
lines changed

‎CHANGELOG.md‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
1414
### Changed
1515

1616
- Updated to stm32-rs v0.6.0 - @HarkonenBade
17+
- Updated the ADC code to use variants added in stm32-rs v0.6.0 - @HarkonenBade
1718

1819
## [v0.12.0] - 2019-01-13
1920

‎src/adc.rs‎

Lines changed: 78 additions & 61 deletions
Original file line numberDiff line numberDiff line change
@@ -49,11 +49,22 @@ use embedded_hal::{
4949
blocking::delay::DelayUs,
5050
};
5151

52-
use crate::{delay::Delay, gpio::*, rcc::Rcc, stm32};
52+
use crate::{
53+
delay::Delay,
54+
gpio::*,
55+
rcc::Rcc,
56+
stm32::{
57+
adc::{
58+
cfgr1::{ALIGNW, RESW},
59+
smpr::SMPW,
60+
},
61+
ADC,
62+
},
63+
};
5364

5465
/// Analog to Digital converter interface
5566
pub struct Adc {
56-
rb: stm32::ADC,
67+
rb: ADC,
5768
sample_time: AdcSampleTime,
5869
align: AdcAlign,
5970
precision: AdcPrecision,
@@ -83,27 +94,27 @@ pub enum AdcSampleTime {
8394
}
8495

8596
impl AdcSampleTime {
86-
fn write_bits(self, adc: &mut stm32::ADC) {
87-
adc.smpr.write(|w| {
88-
w.smp().bits(match self {
89-
AdcSampleTime::T_1 => 0b000_u8,
90-
AdcSampleTime::T_7 => 0b001_u8,
91-
AdcSampleTime::T_13 => 0b010_u8,
92-
AdcSampleTime::T_28 => 0b011_u8,
93-
AdcSampleTime::T_41 => 0b100_u8,
94-
AdcSampleTime::T_55 => 0b101_u8,
95-
AdcSampleTime::T_71 => 0b110_u8,
96-
AdcSampleTime::T_239 => 0b111_u8,
97-
})
98-
});
99-
}
100-
10197
/// Get the default sample time (currently 239.5 cycles)
10298
pub fn default() -> Self {
10399
AdcSampleTime::T_239
104100
}
105101
}
106102

103+
impl From<AdcSampleTime> for SMPW {
104+
fn from(val: AdcSampleTime) -> Self {
105+
match val {
106+
AdcSampleTime::T_1 => SMPW::CYCLES1_5,
107+
AdcSampleTime::T_7 => SMPW::CYCLES7_5,
108+
AdcSampleTime::T_13 => SMPW::CYCLES13_5,
109+
AdcSampleTime::T_28 => SMPW::CYCLES28_5,
110+
AdcSampleTime::T_41 => SMPW::CYCLES41_5,
111+
AdcSampleTime::T_55 => SMPW::CYCLES55_5,
112+
AdcSampleTime::T_71 => SMPW::CYCLES71_5,
113+
AdcSampleTime::T_239 => SMPW::CYCLES239_5,
114+
}
115+
}
116+
}
117+
107118
#[derive(Clone, Copy, Debug, PartialEq)]
108119
/// ADC Result Alignment
109120
pub enum AdcAlign {
@@ -128,22 +139,22 @@ pub enum AdcAlign {
128139
}
129140

130141
impl AdcAlign {
131-
fn write_bits(self, adc: &mut stm32::ADC) {
132-
adc.cfgr1.write(|w| {
133-
w.align().bit(match self {
134-
AdcAlign::Left => true,
135-
AdcAlign::Right => false,
136-
AdcAlign::LeftAsRM => true,
137-
})
138-
});
139-
}
140-
141142
/// Get the default alignment (currently right aligned)
142143
pub fn default() -> Self {
143144
AdcAlign::Right
144145
}
145146
}
146147

148+
impl From<AdcAlign> for ALIGNW {
149+
fn from(val: AdcAlign) -> Self {
150+
match val {
151+
AdcAlign::Left => ALIGNW::LEFT,
152+
AdcAlign::Right => ALIGNW::RIGHT,
153+
AdcAlign::LeftAsRM => ALIGNW::LEFT,
154+
}
155+
}
156+
}
157+
147158
#[derive(Clone, Copy, Debug, PartialEq)]
148159
/// ADC Sampling Precision
149160
pub enum AdcPrecision {
@@ -158,23 +169,23 @@ pub enum AdcPrecision {
158169
}
159170

160171
impl AdcPrecision {
161-
fn write_bits(self, adc: &mut stm32::ADC) {
162-
adc.cfgr1.write(|w| {
163-
w.res().bits(match self {
164-
AdcPrecision::B_12 => 0b00_u8,
165-
AdcPrecision::B_10 => 0b01_u8,
166-
AdcPrecision::B_8 => 0b10_u8,
167-
AdcPrecision::B_6 => 0b11_u8,
168-
})
169-
});
170-
}
171-
172172
/// Get the default precision (currently 12 bit precision)
173173
pub fn default() -> Self {
174174
AdcPrecision::B_12
175175
}
176176
}
177177

178+
impl From<AdcPrecision> for RESW {
179+
fn from(val: AdcPrecision) -> Self {
180+
match val {
181+
AdcPrecision::B_12 => RESW::TWELVEBIT,
182+
AdcPrecision::B_10 => RESW::TENBIT,
183+
AdcPrecision::B_8 => RESW::EIGHTBIT,
184+
AdcPrecision::B_6 => RESW::SIXBIT,
185+
}
186+
}
187+
}
188+
178189
macro_rules! adc_pins {
179190
($($pin:ty => $chan:expr),+ $(,)*) => {
180191
$(
@@ -449,7 +460,7 @@ impl Adc {
449460
/// Sets all configurable parameters to defaults, enables the HSI14 clock
450461
/// for the ADC if it is not already enabled and performs a boot time
451462
/// calibration. As such this method may take an appreciable time to run.
452-
pub fn new(adc: stm32::ADC, rcc: &mut Rcc) -> Self {
463+
pub fn new(adc: ADC, rcc: &mut Rcc) -> Self {
453464
let mut s = Self {
454465
rb: adc,
455466
sample_time: AdcSampleTime::default(),
@@ -532,52 +543,58 @@ impl Adc {
532543

533544
fn calibrate(&mut self) {
534545
/* Ensure that ADEN = 0 */
535-
if self.rb.cr.read().aden().bit_is_set() {
546+
if self.rb.cr.read().aden().is_enabled() {
536547
/* Clear ADEN by setting ADDIS */
537-
self.rb.cr.modify(|_, w| w.addis().set_bit());
548+
self.rb.cr.modify(|_, w| w.addis().disable());
538549
}
539-
while self.rb.cr.read().aden().bit_is_set() {}
550+
while self.rb.cr.read().aden().is_enabled() {}
540551

541552
/* Clear DMAEN */
542-
self.rb.cfgr1.modify(|_, w| w.dmaen().clear_bit());
553+
self.rb.cfgr1.modify(|_, w| w.dmaen().disabled());
543554

544555
/* Start calibration by setting ADCAL */
545-
self.rb.cr.modify(|_, w| w.adcal().set_bit());
556+
self.rb.cr.modify(|_, w| w.adcal().start_calibration());
546557

547558
/* Wait until calibration is finished and ADCAL = 0 */
548-
while self.rb.cr.read().adcal().bit_is_set() {}
559+
while self.rb.cr.read().adcal().is_calibrating() {}
549560
}
550561

551562
fn select_clock(&mut self, rcc: &mut Rcc) {
552-
rcc.regs.apb2enr.modify(|_, w| w.adcen().set_bit());
553-
rcc.regs.cr2.write(|w| w.hsi14on().set_bit());
554-
while rcc.regs.cr2.read().hsi14rdy().bit_is_clear() {}
563+
rcc.regs.apb2enr.modify(|_, w| w.adcen().enabled());
564+
rcc.regs.cr2.write(|w| w.hsi14on().on());
565+
while rcc.regs.cr2.read().hsi14rdy().is_not_ready() {}
555566
}
556567

557568
fn power_up(&mut self) {
558-
if self.rb.isr.read().adrdy().bit_is_set() {
559-
self.rb.isr.modify(|_, w| w.adrdy().clear_bit());
569+
if self.rb.isr.read().adrdy().is_ready() {
570+
self.rb.isr.modify(|_, w| w.adrdy().clear());
560571
}
561-
self.rb.cr.modify(|_, w| w.aden().set_bit());
562-
while self.rb.isr.read().adrdy().bit_is_clear() {}
572+
self.rb.cr.modify(|_, w| w.aden().enabled());
573+
while self.rb.isr.read().adrdy().is_not_ready() {}
563574
}
564575

565576
fn power_down(&mut self) {
566-
self.rb.cr.modify(|_, w| w.adstp().set_bit());
567-
while self.rb.cr.read().adstp().bit_is_set() {}
568-
self.rb.cr.modify(|_, w| w.addis().set_bit());
569-
while self.rb.cr.read().aden().bit_is_set() {}
577+
self.rb.cr.modify(|_, w| w.adstp().stop_conversion());
578+
while self.rb.cr.read().adstp().is_stopping() {}
579+
self.rb.cr.modify(|_, w| w.addis().disable());
580+
while self.rb.cr.read().aden().is_enabled() {}
570581
}
571582

572583
fn convert(&mut self, chan: u8) -> u16 {
573584
self.rb.chselr.write(|w| unsafe { w.bits(1_u32 << chan) });
574585

575-
self.sample_time.write_bits(&mut self.rb);
576-
self.align.write_bits(&mut self.rb);
577-
self.precision.write_bits(&mut self.rb);
586+
self.rb
587+
.smpr
588+
.write(|w| w.smp().variant(self.sample_time.into()));
589+
self.rb.cfgr1.modify(|_, w| {
590+
w.res()
591+
.variant(self.precision.into())
592+
.align()
593+
.variant(self.align.into())
594+
});
578595

579-
self.rb.cr.modify(|_, w| w.adstart().set_bit());
580-
while self.rb.isr.read().eoc().bit_is_clear() {}
596+
self.rb.cr.modify(|_, w| w.adstart().start_conversion());
597+
while self.rb.isr.read().eoc().is_not_complete() {}
581598

582599
let res = self.rb.dr.read().bits() as u16;
583600
if self.align == AdcAlign::Left && self.precision == AdcPrecision::B_6 {

0 commit comments

Comments
 (0)