Update to stm32f0 - 0.6.0 (#52)

* Updated stm32f0 to 0.6.0 and neatened other deps

* Adjusted names and removed unneeded unsafe blocks

* Overhauled RCC to gate HSI48 correctly and add a selector function for it to CFGR

Author: HarkonenBade

CHANGELOG.md

@@ -11,6 +11,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 - Support for stm32f0x8 line - @jessebraham
 
+### Changed
+
+- Updated to stm32-rs v0.6.0 - @HarkonenBade
+
 ## [v0.12.0] - 2019-01-13
 
 ### Added

Cargo.toml

@@ -30,19 +30,13 @@ features = ["stm32f042", "rt"]
 
 [dependencies]
 bare-metal = { version = "0.2.4", features = ["const-fn"] }
+cast = { version = "0.2.2", default-features = false }
 cortex-m = "0.5.8"
 cortex-m-rt = "0.6.7"
+embedded-hal = { version = "0.2.2", features = ["unproven"] }
+stm32f0 = "0.6.0"
 nb = "0.1.1"
 void = { version = "1.0.2", default-features = false }
-stm32f0 = "0.5.0"
-
-[dependencies.cast]
-default-features = false
-version = "0.2.2"
-
-[dependencies.embedded-hal]
-features = ["unproven"]
-version = "0.2.2"
 
 [dev-dependencies]
 panic-halt = "0.2.0"

examples/led_hal_button_irq.rs

@@ -40,7 +40,7 @@ fn main() -> ! {
 
             let gpioa = p.GPIOA.split(&mut rcc);
             let gpiob = p.GPIOB.split(&mut rcc);
-            let syscfg = p.SYSCFG_COMP;
+            let syscfg = p.SYSCFG;
             let exti = p.EXTI;
 
             // Configure PB1 as input (button)
@@ -57,7 +57,7 @@ fn main() -> ! {
 
             // Enable external interrupt for PB1
             syscfg
-                .syscfg_exticr1
+                .exticr1
                 .modify(|_, w| unsafe { w.exti1().bits(1) });
 
             // Set interrupt request mask for line 1

src/adc.rs

@@ -84,20 +84,18 @@ pub enum AdcSampleTime {
 
 impl AdcSampleTime {
     fn write_bits(self, adc: &mut stm32::ADC) {
-        unsafe {
-            adc.smpr.write(|w| {
-                w.smpr().bits(match self {
-                    AdcSampleTime::T_1 => 0b000_u8,
-                    AdcSampleTime::T_7 => 0b001_u8,
-                    AdcSampleTime::T_13 => 0b010_u8,
-                    AdcSampleTime::T_28 => 0b011_u8,
-                    AdcSampleTime::T_41 => 0b100_u8,
-                    AdcSampleTime::T_55 => 0b101_u8,
-                    AdcSampleTime::T_71 => 0b110_u8,
-                    AdcSampleTime::T_239 => 0b111_u8,
-                })
-            });
-        }
+        adc.smpr.write(|w| {
+            w.smp().bits(match self {
+                AdcSampleTime::T_1 => 0b000_u8,
+                AdcSampleTime::T_7 => 0b001_u8,
+                AdcSampleTime::T_13 => 0b010_u8,
+                AdcSampleTime::T_28 => 0b011_u8,
+                AdcSampleTime::T_41 => 0b100_u8,
+                AdcSampleTime::T_55 => 0b101_u8,
+                AdcSampleTime::T_71 => 0b110_u8,
+                AdcSampleTime::T_239 => 0b111_u8,
+            })
+        });
     }
 
     /// Get the default sample time (currently 239.5 cycles)
@@ -161,16 +159,14 @@ pub enum AdcPrecision {
 
 impl AdcPrecision {
     fn write_bits(self, adc: &mut stm32::ADC) {
-        unsafe {
-            adc.cfgr1.write(|w| {
-                w.res().bits(match self {
-                    AdcPrecision::B_12 => 0b00_u8,
-                    AdcPrecision::B_10 => 0b01_u8,
-                    AdcPrecision::B_8 => 0b10_u8,
-                    AdcPrecision::B_6 => 0b11_u8,
-                })
-            });
-        }
+        adc.cfgr1.write(|w| {
+            w.res().bits(match self {
+                AdcPrecision::B_12 => 0b00_u8,
+                AdcPrecision::B_10 => 0b01_u8,
+                AdcPrecision::B_8 => 0b10_u8,
+                AdcPrecision::B_6 => 0b11_u8,
+            })
+        });
     }
 
     /// Get the default precision (currently 12 bit precision)