Skip to content

rustc_target: introduce Arch #147645

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 5 commits into from
Nov 5, 2025
Merged

rustc_target: introduce Arch #147645

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
5 commits
Select commit Hold shift + click to select a range
5e73e65
rename `rustc_target::spec::abi_map::Arch{,Kind}`
tamird Oct 25, 2025
cf053b3
rustc_target::spec::base::apple: nix `use Arch::*`
tamird Oct 25, 2025
270e49b
rustc_target: introduce Arch
tamird Oct 13, 2025
0c8533d
compiler: intern architecture at compile time
tamird Oct 13, 2025
26b0560
rustc_target: allow unenumerated architectures
tamird Oct 28, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
The table of contents is too big for display.
Diff view
Diff view
  •  
  •  
  •  
4 changes: 2 additions & 2 deletions compiler/rustc_attr_parsing/src/attributes/link_attrs.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@ use rustc_hir::attrs::*;
use rustc_session::Session;
use rustc_session::parse::feature_err;
use rustc_span::kw;
use rustc_target::spec::BinaryFormat;
use rustc_target::spec::{Arch, BinaryFormat};

use super::prelude::*;
use super::util::parse_single_integer;
Expand Down Expand Up @@ -438,7 +438,7 @@ impl LinkParser {
cx.expected_name_value(item.span(), Some(sym::import_name_type));
return true;
};
if cx.sess().target.arch != "x86" {
if cx.sess().target.arch != Arch::X86 {
cx.emit_err(ImportNameTypeX86 { span: item.span() });
return true;
}
Expand Down
17 changes: 9 additions & 8 deletions compiler/rustc_codegen_cranelift/src/abi/mod.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@ use rustc_middle::ty::print::with_no_trimmed_paths;
use rustc_session::Session;
use rustc_span::source_map::Spanned;
use rustc_target::callconv::{FnAbi, PassMode};
use rustc_target::spec::Arch;
use smallvec::SmallVec;

use self::pass_mode::*;
Expand Down Expand Up @@ -155,7 +156,7 @@ impl<'tcx> FunctionCx<'_, '_, 'tcx> {
let ret = self.lib_call_unadjusted(name, params, returns, &args)[0];

Cow::Owned(vec![codegen_bitcast(self, types::I128, ret)])
} else if ret_single_i128 && self.tcx.sess.target.arch == "s390x" {
} else if ret_single_i128 && self.tcx.sess.target.arch == Arch::S390x {
// Return i128 using a return area pointer on s390x.
let mut params = params;
let mut args = args.to_vec();
Expand Down Expand Up @@ -641,7 +642,7 @@ pub(crate) fn codegen_terminator_call<'tcx>(
.flat_map(|arg_abi| arg_abi.get_abi_param(fx.tcx).into_iter()),
);

if fx.tcx.sess.target.is_like_darwin && fx.tcx.sess.target.arch == "aarch64" {
if fx.tcx.sess.target.is_like_darwin && fx.tcx.sess.target.arch == Arch::AArch64 {
// Add any padding arguments needed for Apple AArch64.
// There's no need to pad the argument list unless variadic arguments are actually being
// passed.
Expand Down Expand Up @@ -787,25 +788,25 @@ pub(crate) fn codegen_drop<'tcx>(
pub(crate) fn lib_call_arg_param(tcx: TyCtxt<'_>, ty: Type, is_signed: bool) -> AbiParam {
let param = AbiParam::new(ty);
if ty.is_int() && u64::from(ty.bits()) < tcx.data_layout.pointer_size().bits() {
match (&*tcx.sess.target.arch, &*tcx.sess.target.vendor) {
("x86_64", _) | ("aarch64", "apple") => match (ty, is_signed) {
match (&tcx.sess.target.arch, tcx.sess.target.vendor.as_ref()) {
(Arch::X86_64, _) | (Arch::AArch64, "apple") => match (ty, is_signed) {
(types::I8 | types::I16, true) => param.sext(),
(types::I8 | types::I16, false) => param.uext(),
_ => param,
},
("aarch64", _) => param,
("riscv64", _) => match (ty, is_signed) {
(Arch::AArch64, _) => param,
(Arch::RiscV64, _) => match (ty, is_signed) {
(types::I32, _) | (_, true) => param.sext(),
_ => param.uext(),
},
("s390x", _) => {
(Arch::S390x, _) => {
if is_signed {
param.sext()
} else {
param.uext()
}
}
_ => unimplemented!("{:?}", tcx.sess.target.arch),
(arch, _) => unimplemented!("{arch:?}"),
}
} else {
param
Expand Down
10 changes: 7 additions & 3 deletions compiler/rustc_codegen_cranelift/src/codegen_f16_f128.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,8 +1,10 @@
use rustc_target::spec::Arch;

use crate::prelude::*;

pub(crate) fn f16_to_f32(fx: &mut FunctionCx<'_, '_, '_>, value: Value) -> Value {
let (value, arg_ty) =
if fx.tcx.sess.target.vendor == "apple" && fx.tcx.sess.target.arch == "x86_64" {
Copy link
Contributor

@nnethercote nnethercote Oct 28, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Not relevant for this PR, but I wonder if the vendor field would also be better as an enum.

Copy link
Contributor Author

@tamird tamird Oct 28, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Happy to do that next.

if fx.tcx.sess.target.vendor == "apple" && fx.tcx.sess.target.arch == Arch::X86_64 {
(
fx.bcx.ins().bitcast(types::I16, MemFlags::new(), value),
lib_call_arg_param(fx.tcx, types::I16, false),
Expand All @@ -19,7 +21,8 @@ fn f16_to_f64(fx: &mut FunctionCx<'_, '_, '_>, value: Value) -> Value {
}

pub(crate) fn f32_to_f16(fx: &mut FunctionCx<'_, '_, '_>, value: Value) -> Value {
let ret_ty = if fx.tcx.sess.target.vendor == "apple" && fx.tcx.sess.target.arch == "x86_64" {
let ret_ty = if fx.tcx.sess.target.vendor == "apple" && fx.tcx.sess.target.arch == Arch::X86_64
{
types::I16
} else {
types::F16
Expand All @@ -34,7 +37,8 @@ pub(crate) fn f32_to_f16(fx: &mut FunctionCx<'_, '_, '_>, value: Value) -> Value
}

fn f64_to_f16(fx: &mut FunctionCx<'_, '_, '_>, value: Value) -> Value {
let ret_ty = if fx.tcx.sess.target.vendor == "apple" && fx.tcx.sess.target.arch == "x86_64" {
let ret_ty = if fx.tcx.sess.target.vendor == "apple" && fx.tcx.sess.target.arch == Arch::X86_64
{
types::I16
} else {
types::F16
Expand Down
4 changes: 2 additions & 2 deletions compiler/rustc_codegen_cranelift/src/common.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ use rustc_middle::ty::layout::{
};
use rustc_span::source_map::Spanned;
use rustc_target::callconv::FnAbi;
use rustc_target::spec::{HasTargetSpec, Target};
use rustc_target::spec::{Arch, HasTargetSpec, Target};

use crate::constant::ConstantCx;
use crate::debuginfo::FunctionDebugContext;
Expand Down Expand Up @@ -373,7 +373,7 @@ impl<'tcx> FunctionCx<'_, '_, 'tcx> {
"size must be a multiple of alignment (size={size}, align={align})"
);

let abi_align = if self.tcx.sess.target.arch == "s390x" { 8 } else { 16 };
let abi_align = if self.tcx.sess.target.arch == Arch::S390x { 8 } else { 16 };
if align <= abi_align {
let stack_slot = self.bcx.create_sized_stack_slot(StackSlotData {
kind: StackSlotKind::ExplicitSlot,
Expand Down
23 changes: 12 additions & 11 deletions compiler/rustc_codegen_cranelift/src/lib.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -50,6 +50,7 @@ use rustc_middle::dep_graph::{WorkProduct, WorkProductId};
use rustc_session::Session;
use rustc_session::config::OutputFilenames;
use rustc_span::{Symbol, sym};
use rustc_target::spec::Arch;

pub use crate::config::*;
use crate::prelude::*;
Expand Down Expand Up @@ -186,20 +187,20 @@ impl CodegenBackend for CraneliftCodegenBackend {

fn target_config(&self, sess: &Session) -> TargetConfig {
// FIXME return the actually used target features. this is necessary for #[cfg(target_feature)]
let target_features = if sess.target.arch == "x86_64" && sess.target.os != "none" {
// x86_64 mandates SSE2 support and rustc requires the x87 feature to be enabled
vec![sym::fxsr, sym::sse, sym::sse2, Symbol::intern("x87")]
} else if sess.target.arch == "aarch64" {
match &*sess.target.os {
let target_features = match sess.target.arch {
Arch::X86_64 if sess.target.os != "none" => {
// x86_64 mandates SSE2 support and rustc requires the x87 feature to be enabled
vec![sym::fxsr, sym::sse, sym::sse2, Symbol::intern("x87")]
}
Arch::AArch64 => match &*sess.target.os {
"none" => vec![],
// On macOS the aes, sha2 and sha3 features are enabled by default and ring
// fails to compile on macOS when they are not present.
"macos" => vec![sym::neon, sym::aes, sym::sha2, sym::sha3],
// AArch64 mandates Neon support
_ => vec![sym::neon],
}
} else {
vec![]
},
_ => vec![],
};
// FIXME do `unstable_target_features` properly
let unstable_target_features = target_features.clone();
Expand All @@ -208,14 +209,14 @@ impl CodegenBackend for CraneliftCodegenBackend {
// Windows, whereas LLVM 21+ and Cranelift pass it indirectly. This means that `f128` won't
// work when linking against a LLVM-built sysroot.
let has_reliable_f128 = !sess.target.is_like_windows;
let has_reliable_f16 = match &*sess.target.arch {
let has_reliable_f16 = match sess.target.arch {
// FIXME(f16_f128): LLVM 20 does not support `f16` on s390x, meaning the required
// builtins are not available in `compiler-builtins`.
"s390x" => false,
Arch::S390x => false,
// FIXME(f16_f128): `rustc_codegen_llvm` currently disables support on Windows GNU
// targets due to GCC using a different ABI than LLVM. Therefore `f16` won't be
// available when using a LLVM-built sysroot.
"x86_64"
Arch::X86_64
if sess.target.os == "windows"
&& sess.target.env == "gnu"
&& sess.target.abi != "llvm" =>
Expand Down
18 changes: 8 additions & 10 deletions compiler/rustc_codegen_gcc/src/abi.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,8 @@ use rustc_middle::ty::layout::LayoutOf;
#[cfg(feature = "master")]
use rustc_session::config;
use rustc_target::callconv::{ArgAttributes, CastTarget, FnAbi, PassMode};
#[cfg(feature = "master")]
use rustc_target::spec::Arch;

use crate::builder::Builder;
use crate::context::CodegenCx;
Expand Down Expand Up @@ -238,7 +240,7 @@ impl<'gcc, 'tcx> FnAbiGccExt<'gcc, 'tcx> for FnAbi<'tcx, Ty<'tcx>> {
}

#[cfg(feature = "master")]
pub fn conv_to_fn_attribute<'gcc>(conv: CanonAbi, arch: &str) -> Option<FnAttribute<'gcc>> {
pub fn conv_to_fn_attribute<'gcc>(conv: CanonAbi, arch: &Arch) -> Option<FnAttribute<'gcc>> {
let attribute = match conv {
CanonAbi::C | CanonAbi::Rust => return None,
CanonAbi::RustCold => FnAttribute::Cold,
Expand All @@ -251,15 +253,11 @@ pub fn conv_to_fn_attribute<'gcc>(conv: CanonAbi, arch: &str) -> Option<FnAttrib
ArmCall::CCmseNonSecureEntry => FnAttribute::ArmCmseNonsecureEntry,
ArmCall::Aapcs => FnAttribute::ArmPcs("aapcs"),
},
CanonAbi::GpuKernel => {
if arch == "amdgpu" {
FnAttribute::GcnAmdGpuHsaKernel
} else if arch == "nvptx64" {
FnAttribute::NvptxKernel
} else {
panic!("Architecture {} does not support GpuKernel calling convention", arch);
}
}
CanonAbi::GpuKernel => match arch {
&Arch::AmdGpu => FnAttribute::GcnAmdGpuHsaKernel,
&Arch::Nvptx64 => FnAttribute::NvptxKernel,
arch => panic!("Arch {arch} does not support GpuKernel calling convention"),
},
// TODO(antoyo): check if those AVR attributes are mapped correctly.
CanonAbi::Interrupt(interrupt_kind) => match interrupt_kind {
InterruptKind::Avr => FnAttribute::AvrSignal,
Expand Down
8 changes: 5 additions & 3 deletions compiler/rustc_codegen_gcc/src/attributes.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,8 @@ use rustc_middle::middle::codegen_fn_attrs::CodegenFnAttrFlags;
#[cfg(feature = "master")]
use rustc_middle::mir::TerminatorKind;
use rustc_middle::ty;
#[cfg(feature = "master")]
use rustc_target::spec::Arch;

use crate::context::CodegenCx;
use crate::gcc_util::to_gcc_features;
Expand Down Expand Up @@ -70,7 +72,7 @@ fn inline_attr<'gcc, 'tcx>(
InlineAttr::Hint => Some(FnAttribute::Inline),
InlineAttr::Force { .. } => Some(FnAttribute::AlwaysInline),
InlineAttr::Never => {
if cx.sess().target.arch != "amdgpu" {
if cx.sess().target.arch != Arch::AmdGpu {
Some(FnAttribute::NoInline)
} else {
None
Expand Down Expand Up @@ -153,8 +155,8 @@ pub fn from_fn_attrs<'gcc, 'tcx>(
.join(",");
if !target_features.is_empty() {
#[cfg(feature = "master")]
match cx.sess().target.arch.as_ref() {
"x86" | "x86_64" | "powerpc" => {
match cx.sess().target.arch {
Arch::X86 | Arch::X86_64 | Arch::PowerPC => {
func.add_attribute(FnAttribute::Target(&target_features))
}
// The target attribute is not supported on other targets in GCC.
Expand Down
4 changes: 2 additions & 2 deletions compiler/rustc_codegen_gcc/src/base.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -15,9 +15,9 @@ use rustc_middle::mir::mono::Visibility;
use rustc_middle::ty::TyCtxt;
use rustc_session::config::DebugInfo;
use rustc_span::Symbol;
use rustc_target::spec::RelocModel;
#[cfg(feature = "master")]
use rustc_target::spec::SymbolVisibility;
use rustc_target::spec::{Arch, RelocModel};

use crate::builder::Builder;
use crate::context::CodegenCx;
Expand Down Expand Up @@ -116,7 +116,7 @@ pub fn compile_codegen_unit(
.map(|string| &string[1..])
.collect();

if !disabled_features.contains("avx") && tcx.sess.target.arch == "x86_64" {
if !disabled_features.contains("avx") && tcx.sess.target.arch == Arch::X86_64 {
// NOTE: we always enable AVX because the equivalent of llvm.x86.sse2.cmp.pd in GCC for
// SSE2 is multiple builtins, so we use the AVX __builtin_ia32_cmppd instead.
// FIXME(antoyo): use the proper builtins for llvm.x86.sse2.cmp.pd and similar.
Expand Down
68 changes: 36 additions & 32 deletions compiler/rustc_codegen_gcc/src/gcc_util.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,7 @@ use gccjit::Context;
use rustc_codegen_ssa::target_features;
use rustc_data_structures::smallvec::{SmallVec, smallvec};
use rustc_session::Session;
use rustc_target::spec::Arch;

fn gcc_features_by_flags(sess: &Session, features: &mut Vec<String>) {
target_features::retpoline_features_by_flags(sess, features);
Expand Down Expand Up @@ -65,44 +66,47 @@ pub(crate) fn global_gcc_features(sess: &Session, diagnostics: bool) -> Vec<Stri

// To find a list of GCC's names, check https://gcc.gnu.org/onlinedocs/gcc/Function-Attributes.html
pub fn to_gcc_features<'a>(sess: &Session, s: &'a str) -> SmallVec<[&'a str; 2]> {
let arch = if sess.target.arch == "x86_64" { "x86" } else { &*sess.target.arch };
// cSpell:disable
match (arch, s) {
match (&sess.target.arch, s) {
// FIXME: seems like x87 does not exist?
("x86", "x87") => smallvec![],
("x86", "sse4.2") => smallvec!["sse4.2", "crc32"],
("x86", "pclmulqdq") => smallvec!["pclmul"],
("x86", "rdrand") => smallvec!["rdrnd"],
("x86", "bmi1") => smallvec!["bmi"],
("x86", "cmpxchg16b") => smallvec!["cx16"],
("x86", "avx512vaes") => smallvec!["vaes"],
("x86", "avx512gfni") => smallvec!["gfni"],
("x86", "avx512vpclmulqdq") => smallvec!["vpclmulqdq"],
(&Arch::X86 | &Arch::X86_64, "x87") => smallvec![],
(&Arch::X86 | &Arch::X86_64, "sse4.2") => smallvec!["sse4.2", "crc32"],
(&Arch::X86 | &Arch::X86_64, "pclmulqdq") => smallvec!["pclmul"],
(&Arch::X86 | &Arch::X86_64, "rdrand") => smallvec!["rdrnd"],
(&Arch::X86 | &Arch::X86_64, "bmi1") => smallvec!["bmi"],
(&Arch::X86 | &Arch::X86_64, "cmpxchg16b") => smallvec!["cx16"],
(&Arch::X86 | &Arch::X86_64, "avx512vaes") => smallvec!["vaes"],
(&Arch::X86 | &Arch::X86_64, "avx512gfni") => smallvec!["gfni"],
(&Arch::X86 | &Arch::X86_64, "avx512vpclmulqdq") => smallvec!["vpclmulqdq"],
// NOTE: seems like GCC requires 'avx512bw' for 'avx512vbmi2'.
("x86", "avx512vbmi2") => smallvec!["avx512vbmi2", "avx512bw"],
(&Arch::X86 | &Arch::X86_64, "avx512vbmi2") => {
smallvec!["avx512vbmi2", "avx512bw"]
}
// NOTE: seems like GCC requires 'avx512bw' for 'avx512bitalg'.
("x86", "avx512bitalg") => smallvec!["avx512bitalg", "avx512bw"],
("aarch64", "rcpc2") => smallvec!["rcpc-immo"],
("aarch64", "dpb") => smallvec!["ccpp"],
("aarch64", "dpb2") => smallvec!["ccdp"],
("aarch64", "frintts") => smallvec!["fptoint"],
("aarch64", "fcma") => smallvec!["complxnum"],
("aarch64", "pmuv3") => smallvec!["perfmon"],
("aarch64", "paca") => smallvec!["pauth"],
("aarch64", "pacg") => smallvec!["pauth"],
(&Arch::X86 | &Arch::X86_64, "avx512bitalg") => {
smallvec!["avx512bitalg", "avx512bw"]
}
(&Arch::AArch64, "rcpc2") => smallvec!["rcpc-immo"],
(&Arch::AArch64, "dpb") => smallvec!["ccpp"],
(&Arch::AArch64, "dpb2") => smallvec!["ccdp"],
(&Arch::AArch64, "frintts") => smallvec!["fptoint"],
(&Arch::AArch64, "fcma") => smallvec!["complxnum"],
(&Arch::AArch64, "pmuv3") => smallvec!["perfmon"],
(&Arch::AArch64, "paca") => smallvec!["pauth"],
(&Arch::AArch64, "pacg") => smallvec!["pauth"],
// Rust ties fp and neon together. In GCC neon implicitly enables fp,
// but we manually enable neon when a feature only implicitly enables fp
("aarch64", "f32mm") => smallvec!["f32mm", "neon"],
("aarch64", "f64mm") => smallvec!["f64mm", "neon"],
("aarch64", "fhm") => smallvec!["fp16fml", "neon"],
("aarch64", "fp16") => smallvec!["fullfp16", "neon"],
("aarch64", "jsconv") => smallvec!["jsconv", "neon"],
("aarch64", "sve") => smallvec!["sve", "neon"],
("aarch64", "sve2") => smallvec!["sve2", "neon"],
("aarch64", "sve2-aes") => smallvec!["sve2-aes", "neon"],
("aarch64", "sve2-sm4") => smallvec!["sve2-sm4", "neon"],
("aarch64", "sve2-sha3") => smallvec!["sve2-sha3", "neon"],
("aarch64", "sve2-bitperm") => smallvec!["sve2-bitperm", "neon"],
(&Arch::AArch64, "f32mm") => smallvec!["f32mm", "neon"],
(&Arch::AArch64, "f64mm") => smallvec!["f64mm", "neon"],
(&Arch::AArch64, "fhm") => smallvec!["fp16fml", "neon"],
(&Arch::AArch64, "fp16") => smallvec!["fullfp16", "neon"],
(&Arch::AArch64, "jsconv") => smallvec!["jsconv", "neon"],
(&Arch::AArch64, "sve") => smallvec!["sve", "neon"],
(&Arch::AArch64, "sve2") => smallvec!["sve2", "neon"],
(&Arch::AArch64, "sve2-aes") => smallvec!["sve2-aes", "neon"],
(&Arch::AArch64, "sve2-sm4") => smallvec!["sve2-sm4", "neon"],
(&Arch::AArch64, "sve2-sha3") => smallvec!["sve2-sha3", "neon"],
(&Arch::AArch64, "sve2-bitperm") => smallvec!["sve2-bitperm", "neon"],
(_, s) => smallvec![s],
}
// cSpell:enable
Expand Down
4 changes: 2 additions & 2 deletions compiler/rustc_codegen_gcc/src/lib.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -103,7 +103,7 @@ use rustc_middle::util::Providers;
use rustc_session::Session;
use rustc_session::config::{OptLevel, OutputFilenames};
use rustc_span::Symbol;
use rustc_target::spec::RelocModel;
use rustc_target::spec::{Arch, RelocModel};
use tempfile::TempDir;

use crate::back::lto::ModuleBuffer;
Expand Down Expand Up @@ -249,7 +249,7 @@ impl CodegenBackend for GccCodegenBackend {

fn new_context<'gcc, 'tcx>(tcx: TyCtxt<'tcx>) -> Context<'gcc> {
let context = Context::default();
if tcx.sess.target.arch == "x86" || tcx.sess.target.arch == "x86_64" {
if matches!(tcx.sess.target.arch, Arch::X86 | Arch::X86_64) {
context.add_command_line_option("-masm=intel");
}
#[cfg(feature = "master")]
Expand Down
Loading
Loading