@@ -483,7 +483,7 @@ pub trait EvalContextExt<'tcx>: crate::MiriInterpCxExt<'tcx> {
483483 fn apply_events ( & mut self , events : crate :: shims:: trace:: MemEvents ) -> InterpResult < ' tcx > {
484484 let this = self . eval_context_mut ( ) ;
485485 //let accesses = events.accesses;
486- let handle = this. machine . alloc_addresses . borrow ( ) ;
486+ /* let handle = this.machine.alloc_addresses.borrow();
487487 for id in &handle.exposed {
488488 let &base_addr = handle.base_addr.get(id).unwrap();
489489 let info = this.get_alloc_info(*id);
@@ -497,13 +497,22 @@ pub trait EvalContextExt<'tcx>: crate::MiriInterpCxExt<'tcx> {
497497 if info.mutbl.is_not() && acc_kind.did_write() {
498498 throw_ub_format!(""); // TODO: fill this in lol
499499 }
500-
501- if acc_kind. did_write ( ) {
502500
501+ if acc_kind.did_read() {
502+ let src = Pointer::from_addr_invalid(*acc_base);
503+ this.read_immediate_raw(&src);
504+ self.expose_provenance(provenance)
505+ }
506+
507+ if acc_kind.did_write() {
508+ //let alloc = self.alloc_id_from_addr(addr, size, only_exposed_allocations)
503509 }
504510 }
505511 }
506- }
512+ }*/
513+ /*for (acc_base, acc_len, acc_kind) in &events.accesses {
514+ let alloc_id = self.alloc_id_from_addr(addr, size, only_exposed_allocations)
515+ }*/
507516
508517 interp_ok ( ( ) )
509518 }
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