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Implement DPC CSR for RISC-V #368

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Implement DPC CSR for RISC-V #368

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@KushalMeghani1644 KushalMeghani1644 commented Nov 8, 2025

This PR implements the DPC CSR for RISC-V

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@KushalMeghani1644 KushalMeghani1644 requested a review from a team as a code owner November 8, 2025 12:10
romancardenas
romancardenas previously approved these changes Nov 8, 2025
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LGTM

@KushalMeghani1644
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KushalMeghani1644 commented Nov 9, 2025 •
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Great! @romancardenas is there any improvements to be made? or is just a quick merge? :)

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romancardenas commented Nov 9, 2025

Let's leave a few days in case someone from the WG wants to do a second review.

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KushalMeghani1644 commented Nov 9, 2025

Alright! no probs :) either way that would ensure a clean implementation!

rmsyn
rmsyn reviewed Nov 9, 2025
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Small non-blocking suggestions, otherwise LGTM.

riscv/src/register/dpc.rs
read_write_csr! {
/// Debug PC Register
Dpc: 0x7b1,
mask: !1usize,
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What are you basing this alignment on?

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@KushalMeghani1644 KushalMeghani1644 Nov 10, 2025

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The Debug Spec defines dpc as holding the address of the next instruction, and according to the base ISA alignment rules (for the C extension), instruction addresses are always 2-byte aligned.
So, bit 0 of dpc is always 0, which is why the mask !1usize is applied. Hope this clears out what you were concerned about :)

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Update riscv/src/register/dpc.rs
34f2498 
Co-authored-by: rmsyn <117854522+rmsyn@users.noreply.github.com>
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@romancardenas romancardenas romancardenas approved these changes

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