Revise CHANGELOG format and add new entries

Author: KushalMeghani1644

riscv/CHANGELOG.md

@@ -16,7 +16,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ## [v0.15.0] - 2025-09-08
 
 ### Added
-
 - New convenience  `try_new` and `new` associated functions for `Mtvec` and `Stvec`.
 - New methods and functions for enabling core interrupts in the `mie` and `sie` registers
   using the `riscv_pac::CoreInterruptNumber` trait.
@@ -276,6 +275,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ### Changed
 
 - Fixed MSRV by restricting the upper bound of `bare-metal` version
+- Added DCSR (Debug Control and Status Register) CSR support for the RISC-V
 
 [Unreleased]: https://github.com/rust-embedded/riscv/compare/v0.10.1...HEAD
 [v0.10.1]: https://github.com/rust-embedded/riscv/compare/v0.10.0...v0.10.1
@@ -285,4 +285,5 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 [v0.7.0]: https://github.com/rust-embedded/riscv/compare/v0.6.0...v0.7.0
 [v0.6.0]: https://github.com/rust-embedded/riscv/compare/v0.5.6...v0.6.0
 [v0.5.6]: https://github.com/rust-embedded/riscv/compare/v0.5.5...v0.5.6
-[v0.5.5]: https://github.com/rust-embedded/riscv/compare/v0.5.4...v0.5.5
+[v0.5.5]: https://github.com/rust-embedded/riscv/compare/v0.5.4...v0.5.5
+[v0.5.5]: https://github.com/rust-embedded/riscv/compare/v0.5.4...v0.5.5u