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‎CHANGELOG.md‎

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### [Unreleased]
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# Change Log
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All notable changes to this project will be documented in this file.
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The format is based on [Keep a Changelog](http://keepachangelog.com/)
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and this project adheres to [Semantic Versioning](http://semver.org/).
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## [Unreleased]
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## [v0.15.0] - 2025-09-08
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### Added
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- Added DCSR (Debug Control and Status Register) CSR support for the RISC-V
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- New convenience `try_new` and `new` associated functions for `Mtvec` and `Stvec`.
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- New methods and functions for enabling core interrupts in the `mie` and `sie` registers
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using the `riscv_pac::CoreInterruptNumber` trait.
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- New `riscv::interrupt::{is_interrupt_enabled, disable_interrupt, enable_interrupt}` functions.
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- New methods and functions for dealing with pending interrupts in `mip` and `sip` registers
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using the `riscv_pac::CoreInterruptNumber` trait.
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- New `riscv::interrupt::is_interrupt_pending` function.
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- New `riscv::register::xip::clear_pending` atomic function for `mip` and `sip` registers.
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This function is marked as `unsafe`, as its availability depends both on the target chip
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and the target interrupt source.
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- Add `mseccfg` CSR
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- Add `mseccfgh` CSR
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### Changed
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- Use `cfg(any(target_arch = "riscv32", target_arch = "riscv64"))` instead of `cfg(riscv)`.
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- `riscv::pac_enum(unsafe CoreInterrupt)` now locates the vector table at the `.trap.vector`
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section instead of `.trap`.
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- Allow all bits to be set in Mcause::from_bits on 64-bit targets.
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### Removed
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- Removed custom build script, as `cfg(riscv)` is no longer necessary.
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- All the fields of `Mip` and `Sip` CSR proxies are now read-only. This change is motivated
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to avoid clearing unwanted interrupts triggered between CSR reads and CSR writes.
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## [v0.14.0] - 2025-06-10
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### Added
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- CSR helper macro `write_composite_csr` for writing 64-bit CSRs on 32-bit targets.
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- Write utilities for `mcycle`, `minstret`
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- Add `senvcfg` CSR
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- Add `scontext` CSR
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- Add `mconfigptr` CSR
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- Bump MSRV to 1.67.0 for `log` to `ilog` name change
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- Add `mtval2` CSR
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### Changed
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- Simplify `riscv::interrupt::machine::nested`
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## [v0.13.0] - 2025-02-18
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### Added
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- CSR helper macro to check for platform implementation
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### Changed
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- Make all CSR writes `unsafe` by default (#209)
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- Use `RISCV_MTVEC_ALIGN` to control the alignment constraint of the vector table
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- Simplify register macros with `cfg` field
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- Align assembly functions with `cortex-m`
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- Use CSR helper macros to define `marchid` register
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- Re-use `try_*` functions in `mcountinhibit`
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- Use CSR helper macros to define `mcause` register
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- Use CSR helper macros to define `medeleg` register
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- Use CSR helper macros to define `mideleg` register
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- Use CSR helper macros to define `mcounteren` register
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- Use CSR helper macros to define `mie` register
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- Use CSR helper macros to define `mimpid` register
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- Use CSR helper macros to define `misa` register
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- Use CSR helper macros to define `mip` register
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- Use CSR helper macros to define `mstatus` register
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- Use CSR helper macros to define `mstatush` register
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- Use CSR helper macros to define `mtvec` register
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- Use CSR helper macros to define `mtvendorid` register
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- Use CSR helper macros to define `satp` register
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- Use CSR helper macros to define `pmpcfgx` field types
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- Use CSR helper macros to define `scause` field types
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- Use CSR helper macros to define `sie` register
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- Use CSR helper macros to define `scounteren` field types
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- Use CSR helper macros to define `sip` register
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- Use CSR helper macros to define `sstatus` field types
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- Use CSR helper macros to define `stvec` field types
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- Add remaining `pmpcfg` CSRs from RISC-V privileged spec
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## [v0.12.1] - 2024-10-20
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### Changed
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- Update critical-section to 1.2.0
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## [v0.12.0] - 2024-10-19
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### Added
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- `riscv-macros` crate for `riscv-pac` enums.
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- Bump MSRV to 1.61.
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- Implementation of `riscv-pac` traits for `Interrupt` and `Exception` enums.
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- Tests for the `riscv-pac` trait implementations of `Interrupt` and `Exception` enums.
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- Add `Mcause::from(usize)` for use in unit tests
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- Add `Mstatus::from(usize)` for use in unit tests
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- Add `Mstatus.bits()`
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- Add `Eq` and `PartialEq` for `pmpcfgx::{Range, Permission}`
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- Add `Mstatus::update_*` helpers to manipulate Mstatus values without touching
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the CSR
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- Export `riscv::register::macros` module macros for external use
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- Add `riscv::register::mcountinhibit` module for `mcountinhibit` CSR
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- Add `Mcounteren` in-memory update functions
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- Add `Mstatus` vector extension support
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- Add fallible counterparts to all functions that `panic`
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- Add `riscv-pac` as a dependency
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- Add CSR-defining macros to create in-memory types
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### Fixed
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- Fixed `sip::set_ssoft` and `sip::clear_ssoft` using wrong address
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- Fixed assignment in `mstatus` unit tests.
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- delay implementation does not use binary labels in inline assembly.
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## [v0.11.1] - 2024-02-15
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### Changed
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- Made `asm::wfi`, `fence`, `fence_i` and `sfence` safe (ie, removed `unsafe` from their definitions)
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- Made `cfg` variable selection more robust for custom targets
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## [v0.11.0] - 2024-01-14
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### Added
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- Add `asm::ecall()`, a wrapper for implementing an `ecall` instruction
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- Add `nested` function for nested ISRs in `interrupt::machine` and `interrupt::supervisor`
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- `s-mode` feature for reexporting `interrupt::machine` or `interrupt::supervisor` to `interrupt`
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- Support for supervisor-level interrupts in `interrupt::supervisor`
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- Add CI workflow to check that CHANGELOG.md file has been modified in PRs
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- Add `read_csr_as_rv32`, `set_rv32`, and `clear_rv32` macros
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- Add `mstatus::uxl` and `mstatus::sxl`
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- Add `mstatus::ube`, `mstatus::sbe`, and `mstatus::mbe` endianness bit fields
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- Add `mstatush` registers (RISCV-32 only)
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- Add `asm::fence()`, a wrapper for implementing a `fence` instruction
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- Add `asm::fence_i()`, a wrapper for implementing a `fence.i` instruction
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- Add `TryFrom` implementation for `mcause::{Interrupt, Exception}` and `scause::{Interrupt, Exception}`
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### Changed
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- Cargo workspace for riscv and riscv-rt
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- Update `embedded-hal` dependency to v1.0.0 (bumps MSRV to 1.60)
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- `misa::MXL` renamed to `misa::XLEN`
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- Removed `bit_field` dependency
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- CI actions updated. They now use `checkout@v3` and `dtolnay/rust-toolchain`.
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- `mcause::{Interrupt, Exception}` and `scause::{Interrupt, Exception}` now implement `From` trait for `usize`
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- Set safety of `asm::nop` and `asm::delay` functions to safe.
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### Fixed
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- Fix `scause::Exception` missing `LoadMisaligned`
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- Fix `scause::Exception` missing `SupervisorEnvCall`
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- Removed user-level interrupts from `mcause::Interrupt` and `scause::Interrupt`
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- Removed user-level interrupts from `mstatus`
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- Removed machine environment call delegation from `medeleg`
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- Removed user-level interrupts from machine and supervisor mode interrupt-related registers.
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### Removed
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- User mode registers removed, as they are no longer supported in RISC-V
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- FCSR register operations removed to avoid UB (#148)
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## [v0.10.1] - 2023-01-18
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### Fixed
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- Fix implementation for `SingleHartCriticalSection`
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## [v0.10.0] - 2022-11-09
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### Added
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- `critical-section-single-hart` feature which provides an implementation for the `critical_section` crate for single-hart systems, based on disabling all interrupts.
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## [v0.9.0] - 2022-10-06
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### Fixed
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- Fix `asm::delay()` to ensure count register is always reloaded
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- Fix reading marchid and mimpid (#107)
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### Removed
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- `set_msoft`, `clear_msoft`, `set_mtimer` and `clear_mtimer` removed as part of fixing issue #62
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## [v0.8.0] - 2022-04-20
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### Added
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- Add `#[cfg(riscv32)]` to `pmpcfg1` and `pmpcfg3` modules
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- Add enums `Range`, `Permission` for PMP configuration
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- Add `set_pmp()` and `clear_pmp()` functions to pmpcfg(x) modules
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- Add struct `Pmpcsr` and is returned from `pmpcfgx::read()`
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- Add `singleton!` macro
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- Add delay structure and methods using embedded-hal traits and `mcycle` register
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- Add `asm::delay()` function for assembly-based busy-loops
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- Add `asm::nop()`, a wrapper for implementing a `nop` instruction
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- Add missing `#[inline]` attribute to register reads, type conversations and `interrupt::free`
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### Changed
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- Use new `asm!` instead of `llvm_asm!`
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- Change `pmpcfgx::read()` macro to `read_csr_as!()` from `read_csr_as_usize!()`
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- Inline assembly is now always used
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- Update Minimum Supported Rust Version to 1.59
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### Fixed
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- Fix `sfence.vma` operand order
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### Removed
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- Remove `inline-asm` feature which is now always enabled
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## [v0.7.0] - 2021-07-29
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### Added
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- Add `medeleg` register
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- Add `cycle[h]`, `instret[h]` and `mcounteren`
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- Add additional binaries for floating-point ABIs
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- Add support for `mxr`
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- Add support for `mprv`
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### Changed
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- Fix `scause::set`
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- Various formatting and comment fixes
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- Update `bare-metal` to `v1.0.0` removing `Nr` trait
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- Build targets on `docs.rs` are now RISC-V targets other than default ones
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## [v0.6.0] - 2020-06-20
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### Changed
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- `Mtvec::trap_mode()`, `Stvec::trap_mode()` and `Utvec::trap_mode()` functions now return `Option<TrapMode>` (breaking change)
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- Updated Minimum Supported Rust Version to 1.42.0
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- Use `llvm_asm!` instead of `asm!`
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### Removed
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- vexriscv-specific registers were moved to the `vexriscv` crate
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## [v0.5.6] - 2020-03-14
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### Added
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- Added vexriscv-specific registers
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## [v0.5.5] - 2020-02-28
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### Added
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- Added `riscv32i-unknown-none-elf` target support
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- Added user trap setup and handling registers
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- Added write methods for the `mip` and `satp` registers
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- Added `mideleg` register
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- Added Changelog
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### Changed
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- Fixed MSRV by restricting the upper bound of `bare-metal` version
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- Added DCSR (Debug Control and Status Register) CSR support for the RISC-V
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[Unreleased]: https://github.com/rust-embedded/riscv/compare/v0.10.1...HEAD
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[v0.10.1]: https://github.com/rust-embedded/riscv/compare/v0.10.0...v0.10.1
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[v0.10.0]: https://github.com/rust-embedded/riscv/compare/v0.9.0...v0.10.0
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[v0.9.0]: https://github.com/rust-embedded/riscv/compare/v0.8.0...v0.9.0
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[v0.8.0]: https://github.com/rust-embedded/riscv/compare/v0.7.0...v0.8.0
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[v0.7.0]: https://github.com/rust-embedded/riscv/compare/v0.6.0...v0.7.0
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[v0.6.0]: https://github.com/rust-embedded/riscv/compare/v0.5.6...v0.6.0
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[v0.5.6]: https://github.com/rust-embedded/riscv/compare/v0.5.5...v0.5.6
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[v0.5.5]: https://github.com/rust-embedded/riscv/compare/v0.5.4...v0.5.5u

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