Improve parameter name

Author: onethumb

src/algorithm.rs

@@ -325,7 +325,7 @@ where
 unsafe fn fold_and_xor<T: ArchOps, W: EnhancedCrcWidth>(
     current: T::Vector,
     coefficient: T::Vector,
-    new_data: T::Vector,
+    data_to_xor: T::Vector,
     reflected: bool,
     ops: &T,
 ) -> T::Vector
@@ -339,7 +339,7 @@ where
     };
 
     // Fold 16 bytes using width-specific method
-    W::fold_16(&mut temp_state, coefficient, new_data, ops);
+    W::fold_16(&mut temp_state, coefficient, data_to_xor, ops);
 
     temp_state.value
 }

src/arch/vpclmulqdq.rs

@@ -38,12 +38,12 @@ impl Simd256 {
 
     #[inline]
     #[target_feature(enable = "avx2,avx512f,avx512vl,vpclmulqdq")]
-    unsafe fn fold_32(&self, coeff: &Self, new_data: &Self) -> Self {
+    unsafe fn fold_32(&self, coeff: &Self, data_to_xor: &Self) -> Self {
         // XOR3
         Self(_mm256_ternarylogic_epi64(
             _mm256_clmulepi64_epi128(self.0, coeff.0, 0x00),
             _mm256_clmulepi64_epi128(self.0, coeff.0, 0x11),
-            new_data.0,
+            data_to_xor.0,
             0x96,
         ))
     }

src/arch/x86.rs

@@ -244,7 +244,9 @@ impl ArchOps for X86Ops {
     ) -> Self::Vector {
         #[cfg(any(feature = "vpclmulqdq", feature = "avx512"))]
         if is_x86_feature_detected!("avx512f") && is_x86_feature_detected!("avx512vl") {
-            return _mm_ternarylogic_epi64(a, b, c, 0x96);
+            return _mm_ternarylogic_epi64(
+                a, b, c, 0x96, // XOR3
+            );
         }
 
         // x86 doesn't have native XOR3 in SSE, use two XORs

src/crc32/algorithm.rs

@@ -79,7 +79,7 @@ impl EnhancedCrcWidth for crate::structs::Width32 {
     unsafe fn fold_16<T: ArchOps>(
         state: &mut CrcState<T::Vector>,
         coeff: T::Vector,
-        new_data: T::Vector,
+        data_to_xor: T::Vector,
         ops: &T,
     ) where
         T::Vector: Copy,
@@ -99,7 +99,7 @@ impl EnhancedCrcWidth for crate::structs::Width32 {
             )
         };
 
-        state.value = ops.xor3_vectors(h, l, new_data);
+        state.value = ops.xor3_vectors(h, l, data_to_xor);
     }
 
     /// CRC-32 specific implementation for folding 8 bytes to 4 bytes

src/crc64/algorithm.rs

@@ -60,7 +60,7 @@ impl EnhancedCrcWidth for crate::structs::Width64 {
     unsafe fn fold_16<T: ArchOps>(
         state: &mut CrcState<T::Vector>,
         coeff: T::Vector,
-        new_data: T::Vector,
+        data_to_xor: T::Vector,
         ops: &T,
     ) where
         T::Vector: Copy,
@@ -70,7 +70,7 @@ impl EnhancedCrcWidth for crate::structs::Width64 {
             ops.xor3_vectors(
                 ops.carryless_mul_00(state.value, coeff),
                 ops.carryless_mul_11(state.value, coeff),
-                new_data,
+                data_to_xor,
             )
         };
     }

src/traits.rs

@@ -260,7 +260,7 @@ pub trait EnhancedCrcWidth: CrcWidth {
     unsafe fn fold_16<T: ArchOps>(
         state: &mut CrcState<T::Vector>,
         coefficient: T::Vector,
-        new_data: T::Vector,
+        data_to_xor: T::Vector,
         ops: &T,
     ) where
         T::Vector: Copy;