Make InterruptArray an argument

Author: ALSchwalm

mythril/src/emulate/memio.rs

@@ -9,6 +9,7 @@ fn emulate_outs(
     port: Port,
     guest_cpu: &mut vmexit::GuestCpuState,
     exit: vmexit::IoInstructionInformation,
+    interrupts: &mut InterruptArray,
 ) -> Result<()> {
     let mut vm = vcpu.vm.write();
 
@@ -34,22 +35,13 @@ fn emulate_outs(
     )?;
 
     // FIXME: Actually test for REP
-    let mut interrupts = InterruptArray::default();
     for chunk in bytes.chunks_exact(exit.size as usize) {
         let request = PortWriteRequest::try_from(chunk)?;
-        interrupts = vm.on_port_write(vcpu, port, request)?;
+        vm.on_port_write(vcpu, port, request, interrupts)?;
     }
 
     guest_cpu.rsi += bytes.len() as u64;
     guest_cpu.rcx = 0;
-    drop(vm);
-
-    for interrupt in interrupts {
-        vcpu.inject_interrupt(
-            interrupt,
-            vcpu::InjectedInterruptType::ExternalInterrupt,
-        );
-    }
     Ok(())
 }
 
@@ -58,6 +50,7 @@ fn emulate_ins(
     port: Port,
     guest_cpu: &mut vmexit::GuestCpuState,
     exit: vmexit::IoInstructionInformation,
+    interrupts: &mut InterruptArray,
 ) -> Result<()> {
     let mut vm = vcpu.vm.write();
 
@@ -67,12 +60,9 @@ fn emulate_ins(
     let access = memory::GuestAccess::Read(memory::PrivilegeLevel(0));
 
     let mut bytes = vec![0u8; guest_cpu.rcx as usize];
-    let mut interrupts = InterruptArray::default();
     for chunk in bytes.chunks_exact_mut(exit.size as usize) {
         let request = PortReadRequest::try_from(chunk)?;
-
-        //TODO: For now, only consider the _last_ interrupt/exception/fault
-        interrupts = vm.on_port_read(vcpu, port, request)?;
+        vm.on_port_read(vcpu, port, request, interrupts)?;
     }
 
     let mut view = memory::GuestAddressSpaceViewMut::from_vmcs(
@@ -83,57 +73,43 @@ fn emulate_ins(
 
     guest_cpu.rdi += bytes.len() as u64;
     guest_cpu.rcx = 0;
-    drop(vm);
-
-    for interrupt in interrupts {
-        vcpu.inject_interrupt(
-            interrupt,
-            vcpu::InjectedInterruptType::ExternalInterrupt,
-        );
-    }
     Ok(())
 }
 
 pub fn emulate_portio(
     vcpu: &mut vcpu::VCpu,
     guest_cpu: &mut vmexit::GuestCpuState,
     exit: vmexit::IoInstructionInformation,
+    interrupts: &mut InterruptArray,
 ) -> Result<()> {
     let (port, input, size, string) =
         (exit.port, exit.input, exit.size, exit.string);
 
     if !string {
         let mut vm = vcpu.vm.write();
-
-        let interrupts = if !input {
+        if !input {
             let arr = (guest_cpu.rax as u32).to_be_bytes();
             vm.on_port_write(
                 vcpu,
                 port,
                 PortWriteRequest::try_from(&arr[4 - size as usize..])?,
-            )?
+                interrupts,
+            )?;
         } else {
             let mut arr = [0u8; 4];
             let request =
                 PortReadRequest::try_from(&mut arr[4 - size as usize..])?;
-            let interrupts = vm.on_port_read(vcpu, port, request)?;
+            vm.on_port_read(vcpu, port, request, interrupts)?;
             guest_cpu.rax &= (!guest_cpu.rax) << (size * 8);
             guest_cpu.rax |= u32::from_be_bytes(arr) as u64;
-            interrupts
         };
-        drop(vm);
-        for interrupt in interrupts {
-            vcpu.inject_interrupt(
-                interrupt,
-                vcpu::InjectedInterruptType::ExternalInterrupt,
-            );
-        }
     } else {
         if !input {
-            emulate_outs(vcpu, port, guest_cpu, exit)?;
+            emulate_outs(vcpu, port, guest_cpu, exit, interrupts)?;
         } else {
-            emulate_ins(vcpu, port, guest_cpu, exit)?;
+            emulate_ins(vcpu, port, guest_cpu, exit, interrupts)?;
         }
     }
+
     Ok(())
 }

mythril/src/emulate/portio.rs

@@ -189,31 +189,12 @@ fault_fn!(zero_division_handler, state, {
     panic!("Divide by zero handler (rip=0x{:x})", state.rip);
 });
 
-interrupt_fn!(ps2_input_handler, state, {
-    use x86::io::{inb, outb};
-
-    let input = inb(0x60);
-    let status = inb(0x64);
-    info!("Key 0x{:x} pressed (status = 0x{:x})", input, status);
-    outb(0x20, 0x20);
-});
-
-interrupt_fn!(uart_input_handler, state, {
-    use x86::io::{inb, outb};
-
-    info!("Uart input");
-    outb(0x20, 0x20);
-});
-
 pub unsafe fn init() {
     IDT[0].set_func(zero_division_handler);
     IDT[2].set_func(nmi_handler);
     IDT[13].set_func(protection_fault_handler);
     IDT[14].set_func(page_fault_handler);
 
-    // IDT[33].set_func(ps2_input_handler);
-    // IDT[36].set_func(uart_input_handler);
-
     ap_init();
 }
 

mythril/src/interrupt/idt.rs

@@ -32,19 +32,35 @@ fn default_vm(
     core: usize,
     mem: u64,
     info: &BootInfo,
+    add_uart: bool,
 ) -> Arc<RwLock<vm::VirtualMachine>> {
-    let mut config = vm::VirtualMachineConfig::new(vec![core as u8], mem);
+    let physical_config = if add_uart == false {
+        vm::PhysicalDeviceConfig::default()
+    } else {
+        vm::PhysicalDeviceConfig {
+            serial: Some(
+                physdev::com::Uart8250::new(0x3f8)
+                    .expect("Failed to create UART"),
+            ),
+        }
+    };
+
+    let mut config =
+        vm::VirtualMachineConfig::new(vec![core as u8], mem, physical_config);
 
     // FIXME: When `map_bios` may return an error, log the error.
     config.map_bios("seabios.bin".into()).unwrap_or(());
 
-    let device_map = config.device_map();
+    let device_map = config.virtual_devices_mut();
     device_map
         .register_device(virtdev::acpi::AcpiRuntime::new(0xb000).unwrap())
         .unwrap();
     device_map
         .register_device(virtdev::debug::DebugPort::new(core as u64, 0x402))
         .unwrap();
+    device_map
+        .register_device(virtdev::com::Uart8250::new(core as u64, 0x3F8))
+        .unwrap();
     device_map
         .register_device(virtdev::vga::VgaController::new())
         .unwrap();
@@ -161,11 +177,6 @@ unsafe fn kmain(mut boot_info: BootInfo) -> ! {
 
     // physdev::keyboard::Ps2Controller::init().expect("Failed to init ps2 controller");
 
-    // let uart = physdev::com::Uart8250::new(0x3f8);
-    // unsafe {interrupt::enable_interrupts()};
-
-    // loop {}
-
     // If the boot method provided an RSDT, use that one. Otherwise, search the
     // BIOS areas for it.
     let rsdt = boot_info
@@ -202,64 +213,64 @@ unsafe fn kmain(mut boot_info: BootInfo) -> ! {
     for apic_id in apic_ids.iter() {
         map.insert(
             *apic_id as usize,
-            default_vm(*apic_id as usize, 256, &boot_info),
+            default_vm(*apic_id as usize, 256, &boot_info, *apic_id == 0),
         );
     }
 
     vm::VM_MAP = Some(map);
 
     debug!("AP_STARTUP address: 0x{:x}", AP_STARTUP_ADDR);
 
-    // for (idx, apic_id) in apic_ids.into_iter().enumerate() {
-    //     if apic_id == local_apic.id() as u32 {
-    //         continue;
-    //     }
-
-    //     // Allocate a stack for the AP
-    //     let stack = vec![0u8; 100 * 1024];
-
-    //     // Get the the bottom of the stack and align
-    //     let stack_bottom =
-    //         (stack.as_ptr() as u64 + stack.len() as u64) & 0xFFFFFFFFFFFFFFF0;
-
-    //     core::mem::forget(stack);
-
-    //     core::ptr::write_volatile(&mut AP_STACK_ADDR as *mut u64, stack_bottom);
-
-    //     // Map the APIC ids to a sequential list and pass it to the AP
-    //     core::ptr::write_volatile(&mut AP_IDX as *mut u64, idx as u64);
-
-    //     // mfence to ensure that the APs see the new stack address
-    //     core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst);
-
-    //     debug!("Send INIT to AP id={}", apic_id);
-    //     local_apic.send_ipi(
-    //         apic_id,
-    //         apic::DstShorthand::NoShorthand,
-    //         apic::TriggerMode::Edge,
-    //         apic::Level::Assert,
-    //         apic::DstMode::Physical,
-    //         apic::DeliveryMode::Init,
-    //         0,
-    //     );
-
-    //     debug!("Send SIPI to AP id={}", apic_id);
-    //     local_apic.send_ipi(
-    //         apic_id,
-    //         apic::DstShorthand::NoShorthand,
-    //         apic::TriggerMode::Edge,
-    //         apic::Level::Assert,
-    //         apic::DstMode::Physical,
-    //         apic::DeliveryMode::StartUp,
-    //         (AP_STARTUP_ADDR >> 12) as u8,
-    //     );
-
-    //     // Wait until the AP reports that it is done with startup
-    //     while core::ptr::read_volatile(&AP_READY as *const u8) != 1 {}
-
-    //     // Once the AP is done, clear the ready flag
-    //     core::ptr::write_volatile(&mut AP_READY as *mut u8, 0);
-    // }
+    for (idx, apic_id) in apic_ids.into_iter().enumerate() {
+        if apic_id == local_apic.id() as u32 {
+            continue;
+        }
+
+        // Allocate a stack for the AP
+        let stack = vec![0u8; 100 * 1024];
+
+        // Get the the bottom of the stack and align
+        let stack_bottom =
+            (stack.as_ptr() as u64 + stack.len() as u64) & 0xFFFFFFFFFFFFFFF0;
+
+        core::mem::forget(stack);
+
+        core::ptr::write_volatile(&mut AP_STACK_ADDR as *mut u64, stack_bottom);
+
+        // Map the APIC ids to a sequential list and pass it to the AP
+        core::ptr::write_volatile(&mut AP_IDX as *mut u64, idx as u64);
+
+        // mfence to ensure that the APs see the new stack address
+        core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst);
+
+        debug!("Send INIT to AP id={}", apic_id);
+        local_apic.send_ipi(
+            apic_id,
+            apic::DstShorthand::NoShorthand,
+            apic::TriggerMode::Edge,
+            apic::Level::Assert,
+            apic::DstMode::Physical,
+            apic::DeliveryMode::Init,
+            0,
+        );
+
+        debug!("Send SIPI to AP id={}", apic_id);
+        local_apic.send_ipi(
+            apic_id,
+            apic::DstShorthand::NoShorthand,
+            apic::TriggerMode::Edge,
+            apic::Level::Assert,
+            apic::DstMode::Physical,
+            apic::DeliveryMode::StartUp,
+            (AP_STARTUP_ADDR >> 12) as u8,
+        );
+
+        // Wait until the AP reports that it is done with startup
+        while core::ptr::read_volatile(&AP_READY as *const u8) != 1 {}
+
+        // Once the AP is done, clear the ready flag
+        core::ptr::write_volatile(&mut AP_READY as *mut u8, 0);
+    }
 
     vcpu::mp_entry_point()
 }

mythril/src/kmain.rs

@@ -55,6 +55,10 @@ impl Uart8250 {
         Ok(uart)
     }
 
+    pub fn base_port(&self) -> u16 {
+        self.base
+    }
+
     fn read_ier(&self) -> IerFlags {
         IerFlags::from_bits_truncate(unsafe {
             inb(self.base + SerialOffset::IER)

mythril/src/physdev/com.rs

@@ -93,11 +93,6 @@ impl Ps2Controller {
         }
 
         Self::flush_read("init finished");
-
-        // info!("{:?}", Self::read_status_port());
-        // info!("{:?}", Self::read_configuration());
-        // Self::write_command_port(Command::EnableFirst);
-        info!("Done with ps2 initialization");
         Ok(())
     }
 
@@ -152,12 +147,4 @@ impl Ps2Controller {
             outb(PS2_COMMAND_PORT, cmd as u8);
         }
     }
-
-    fn output_available() -> bool {
-        Self::read_status_port().contains(Ps2StatusFlags::OUTPUT_BUFFER_FULL)
-    }
-
-    fn ready_for_input() -> bool {
-        !Self::read_status_port().contains(Ps2StatusFlags::INPUT_BUFFER_FULL)
-    }
 }