Basic input working

Author: ALSchwalm

mythril/src/boot.S

@@ -148,10 +148,36 @@ _start:
     call map_page_directory
     pop edi
 
-    ; Disable IRQs (probably not necessary)
-    mov al, 0xFF                      ; Out 0xFF to 0xA1 and 0x21 to disable all IRQs.
-    out 0xA1, al
+    ; Setup PIC
+    mov al, 0x11
+    out 0x20, al
+    out 0xa0, al
+
+    ; Setup offsets
+    mov al, 0x20
+    out 0x21, al
+    mov al, 0x28
+    out 0xa1, al
+
+    mov al, 0x4
+    out 0x21, al
+    mov al, 0x2
+    out 0xa1, al
+
+    mov al, 0x1
+    out 0x21, al
+    out 0xa1, al
+
+    ; Set IRQ masks
+    mov al, 0xED                ; Unmask IRQ1 (ps2) and IRQ4 (COM1)
     out 0x21, al
+    mov al, 0xFF
+    out 0xA1, al
+
+    ; ACK any pending interrupts
+    mov al, 0x20
+    out 0x20, al
+    out 0xa0, al
 
     ; Enter long mode.
     mov eax, 10100000b                ; Set the PAE and PGE bit.

mythril/src/emulate/memio.rs

@@ -1,6 +1,6 @@
-use crate::device::{MemReadRequest, MemWriteRequest};
 use crate::error::{Error, Result};
 use crate::memory;
+use crate::virtdev::{MemReadRequest, MemWriteRequest};
 use crate::{vcpu, vmcs, vmexit};
 use arrayvec::ArrayVec;
 use iced_x86;

mythril/src/emulate/portio.rs

@@ -1,6 +1,6 @@
-use crate::device::{InterruptArray, Port, PortReadRequest, PortWriteRequest};
 use crate::error::Result;
 use crate::memory;
+use crate::virtdev::{InterruptArray, Port, PortReadRequest, PortWriteRequest};
 use crate::{vcpu, vmcs, vmexit};
 use core::convert::TryFrom;
 

mythril/src/interrupt/idt.rs

@@ -189,12 +189,31 @@ fault_fn!(zero_division_handler, state, {
     panic!("Divide by zero handler (rip=0x{:x})", state.rip);
 });
 
+interrupt_fn!(ps2_input_handler, state, {
+    use x86::io::{inb, outb};
+
+    let input = inb(0x60);
+    let status = inb(0x64);
+    info!("Key 0x{:x} pressed (status = 0x{:x})", input, status);
+    outb(0x20, 0x20);
+});
+
+interrupt_fn!(uart_input_handler, state, {
+    use x86::io::{inb, outb};
+
+    info!("Uart input");
+    outb(0x20, 0x20);
+});
+
 pub unsafe fn init() {
     IDT[0].set_func(zero_division_handler);
     IDT[2].set_func(nmi_handler);
     IDT[13].set_func(protection_fault_handler);
     IDT[14].set_func(page_fault_handler);
 
+    // IDT[33].set_func(ps2_input_handler);
+    // IDT[36].set_func(uart_input_handler);
+
     ap_init();
 }
 

mythril/src/kmain.rs

@@ -2,15 +2,16 @@ use crate::acpi;
 use crate::ap;
 use crate::apic;
 use crate::boot_info::BootInfo;
-use crate::device;
 use crate::interrupt;
 use crate::linux;
 use crate::logger;
 use crate::memory;
 use crate::multiboot2;
 use crate::percore;
+use crate::physdev;
 use crate::time;
 use crate::vcpu;
+use crate::virtdev;
 use crate::vm;
 
 use alloc::collections::BTreeMap;
@@ -39,57 +40,45 @@ fn default_vm(
 
     let device_map = config.device_map();
     device_map
-        .register_device(device::acpi::AcpiRuntime::new(0xb000).unwrap())
+        .register_device(virtdev::acpi::AcpiRuntime::new(0xb000).unwrap())
         .unwrap();
     device_map
-        .register_device(device::com::ComDevice::new(core as u64, 0x3F8))
+        .register_device(virtdev::debug::DebugPort::new(core as u64, 0x402))
         .unwrap();
     device_map
-        .register_device(device::com::ComDevice::new(core as u64, 0x2F8))
+        .register_device(virtdev::vga::VgaController::new())
         .unwrap();
     device_map
-        .register_device(device::com::ComDevice::new(core as u64, 0x3E8))
+        .register_device(virtdev::dma::Dma8237::new())
         .unwrap();
     device_map
-        .register_device(device::com::ComDevice::new(core as u64, 0x2E8))
+        .register_device(virtdev::ignore::IgnoredDevice::new())
         .unwrap();
     device_map
-        .register_device(device::debug::DebugPort::new(core as u64, 0x402))
+        .register_device(virtdev::pci::PciRootComplex::new())
         .unwrap();
     device_map
-        .register_device(device::vga::VgaController::new())
+        .register_device(virtdev::pic::Pic8259::new())
         .unwrap();
     device_map
-        .register_device(device::dma::Dma8237::new())
+        .register_device(virtdev::keyboard::Keyboard8042::new())
         .unwrap();
     device_map
-        .register_device(device::ignore::IgnoredDevice::new())
+        .register_device(virtdev::pit::Pit8254::new())
         .unwrap();
     device_map
-        .register_device(device::pci::PciRootComplex::new())
+        .register_device(virtdev::pos::ProgrammableOptionSelect::new())
         .unwrap();
     device_map
-        .register_device(device::pic::Pic8259::new())
-        .unwrap();
-    device_map
-        .register_device(device::keyboard::Keyboard8042::new())
-        .unwrap();
-    device_map
-        .register_device(device::pit::Pit8254::new())
-        .unwrap();
-    device_map
-        .register_device(device::pos::ProgrammableOptionSelect::new())
-        .unwrap();
-    device_map
-        .register_device(device::rtc::CmosRtc::new(mem))
+        .register_device(virtdev::rtc::CmosRtc::new(mem))
         .unwrap();
 
     //TODO: this should actually be per-vcpu
     device_map
-        .register_device(device::lapic::LocalApic::new())
+        .register_device(virtdev::lapic::LocalApic::new())
         .unwrap();
 
-    let mut fw_cfg_builder = device::qemu_fw_cfg::QemuFwCfgBuilder::new();
+    let mut fw_cfg_builder = virtdev::qemu_fw_cfg::QemuFwCfgBuilder::new();
 
     // The 'linuxboot' file is an option rom that loads the linux kernel
     // via qemu_fw_cfg
@@ -116,7 +105,7 @@ fn default_vm(
             "rodata=0 nopti disableapic acpi=off ",
             "earlyprintk=serial,0x3f8,115200 ",
             "console=ttyS0 debug nokaslr noapic mitigations=off ",
-            "root=/dev/ram0 rdinit=/init\0"
+            "root=/dev/ram0 rdinit=/bin/sh\0"
         )
         .as_bytes(),
         mem,
@@ -143,6 +132,8 @@ pub extern "C" fn ap_entry(_ap_data: &ap::ApData) -> ! {
         local_apic.version()
     );
 
+    unsafe { interrupt::enable_interrupts() };
+
     vcpu::mp_entry_point()
 }
 
@@ -168,6 +159,13 @@ unsafe fn kmain(mut boot_info: BootInfo) -> ! {
     // Calibrate the global time source
     time::init_global_time().expect("Failed to init global timesource");
 
+    // physdev::keyboard::Ps2Controller::init().expect("Failed to init ps2 controller");
+
+    // let uart = physdev::com::Uart8250::new(0x3f8);
+    // unsafe {interrupt::enable_interrupts()};
+
+    // loop {}
+
     // If the boot method provided an RSDT, use that one. Otherwise, search the
     // BIOS areas for it.
     let rsdt = boot_info
@@ -212,56 +210,56 @@ unsafe fn kmain(mut boot_info: BootInfo) -> ! {
 
     debug!("AP_STARTUP address: 0x{:x}", AP_STARTUP_ADDR);
 
-    for (idx, apic_id) in apic_ids.into_iter().enumerate() {
-        if apic_id == local_apic.id() as u32 {
-            continue;
-        }
-
-        // Allocate a stack for the AP
-        let stack = vec![0u8; 100 * 1024];
-
-        // Get the the bottom of the stack and align
-        let stack_bottom =
-            (stack.as_ptr() as u64 + stack.len() as u64) & 0xFFFFFFFFFFFFFFF0;
-
-        core::mem::forget(stack);
-
-        core::ptr::write_volatile(&mut AP_STACK_ADDR as *mut u64, stack_bottom);
-
-        // Map the APIC ids to a sequential list and pass it to the AP
-        core::ptr::write_volatile(&mut AP_IDX as *mut u64, idx as u64);
-
-        // mfence to ensure that the APs see the new stack address
-        core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst);
-
-        debug!("Send INIT to AP id={}", apic_id);
-        local_apic.send_ipi(
-            apic_id,
-            apic::DstShorthand::NoShorthand,
-            apic::TriggerMode::Edge,
-            apic::Level::Assert,
-            apic::DstMode::Physical,
-            apic::DeliveryMode::Init,
-            0,
-        );
-
-        debug!("Send SIPI to AP id={}", apic_id);
-        local_apic.send_ipi(
-            apic_id,
-            apic::DstShorthand::NoShorthand,
-            apic::TriggerMode::Edge,
-            apic::Level::Assert,
-            apic::DstMode::Physical,
-            apic::DeliveryMode::StartUp,
-            (AP_STARTUP_ADDR >> 12) as u8,
-        );
-
-        // Wait until the AP reports that it is done with startup
-        while core::ptr::read_volatile(&AP_READY as *const u8) != 1 {}
-
-        // Once the AP is done, clear the ready flag
-        core::ptr::write_volatile(&mut AP_READY as *mut u8, 0);
-    }
+    // for (idx, apic_id) in apic_ids.into_iter().enumerate() {
+    //     if apic_id == local_apic.id() as u32 {
+    //         continue;
+    //     }
+
+    //     // Allocate a stack for the AP
+    //     let stack = vec![0u8; 100 * 1024];
+
+    //     // Get the the bottom of the stack and align
+    //     let stack_bottom =
+    //         (stack.as_ptr() as u64 + stack.len() as u64) & 0xFFFFFFFFFFFFFFF0;
+
+    //     core::mem::forget(stack);
+
+    //     core::ptr::write_volatile(&mut AP_STACK_ADDR as *mut u64, stack_bottom);
+
+    //     // Map the APIC ids to a sequential list and pass it to the AP
+    //     core::ptr::write_volatile(&mut AP_IDX as *mut u64, idx as u64);
+
+    //     // mfence to ensure that the APs see the new stack address
+    //     core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst);
+
+    //     debug!("Send INIT to AP id={}", apic_id);
+    //     local_apic.send_ipi(
+    //         apic_id,
+    //         apic::DstShorthand::NoShorthand,
+    //         apic::TriggerMode::Edge,
+    //         apic::Level::Assert,
+    //         apic::DstMode::Physical,
+    //         apic::DeliveryMode::Init,
+    //         0,
+    //     );
+
+    //     debug!("Send SIPI to AP id={}", apic_id);
+    //     local_apic.send_ipi(
+    //         apic_id,
+    //         apic::DstShorthand::NoShorthand,
+    //         apic::TriggerMode::Edge,
+    //         apic::Level::Assert,
+    //         apic::DstMode::Physical,
+    //         apic::DeliveryMode::StartUp,
+    //         (AP_STARTUP_ADDR >> 12) as u8,
+    //     );
+
+    //     // Wait until the AP reports that it is done with startup
+    //     while core::ptr::read_volatile(&AP_READY as *const u8) != 1 {}
+
+    //     // Once the AP is done, clear the ready flag
+    //     core::ptr::write_volatile(&mut AP_READY as *mut u8, 0);
+    // }
 
     vcpu::mp_entry_point()
 }

mythril/src/lib.rs

@@ -28,10 +28,10 @@ pub mod ap;
 /// Support for the local APIC.
 pub mod apic;
 pub mod boot_info;
-pub mod device;
+
 pub mod emulate;
 pub mod error;
-mod global_alloc;
+pub mod global_alloc;
 pub mod interrupt;
 pub mod ioapic;
 pub mod kmain;
@@ -40,12 +40,13 @@ pub mod logger;
 pub mod memory;
 pub mod multiboot2;
 pub mod percore;
-pub mod pit;
-mod registers;
+pub mod physdev;
+pub mod registers;
 pub mod time;
 pub mod tsc;
 pub mod vcpu;
+pub mod virtdev;
 pub mod vm;
 pub mod vmcs;
-mod vmexit;
+pub mod vmexit;
 pub mod vmx;

mythril/src/linux.rs

@@ -1,6 +1,6 @@
 use crate::boot_info::BootInfo;
-use crate::device::qemu_fw_cfg::{FwCfgSelector, QemuFwCfgBuilder};
 use crate::error::{Error, Result};
+use crate::virtdev::qemu_fw_cfg::{FwCfgSelector, QemuFwCfgBuilder};
 use bitflags::bitflags;
 use byteorder::{ByteOrder, LittleEndian};