Skip to content

Commit 49afbf4

Browse files
maksyukimaksyuki
committed
refactor: add equation to calc the offset and mask
1 parent 84fdd40 commit 49afbf4

File tree

2 files changed

+46
-41
lines changed

2 files changed

+46
-41
lines changed

‎rtl/tc_l2/src/main/scala/axi4/AXI4Bridge.scala‎

Lines changed: 45 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,7 @@ object AXI4Bridge {
6363
val SIZE_D = "b11".U(2.W)
6464
}
6565

66-
class AXI4Bridge() extends Module with AXI4Config with InstConfig {
66+
class AXI4Bridge() extends Module with AXI4Config {
6767
val io = IO(new Bundle {
6868
val inst: AXI4USERIO = new AXI4USERIO
6969
val mem: AXI4USERIO = new AXI4USERIO
@@ -284,26 +284,31 @@ class AXI4Bridge() extends Module with AXI4Config with InstConfig {
284284
}
285285

286286
// ------------------Process Data------------------
287-
protected val ALIGNED_WIDTH = 3 // eval: log2(AxiDataWidth / 8)
288-
protected val OFFSET_WIDTH = 6 // eval: log2(AxiDataWidth)
289-
protected val AXI_INST_SIZE = if (SoCEna) 2.U else 3.U // because the flash only support 4 bytes access
290-
protected val MASK_WIDTH = 128 // eval: AxiDataWidth * 2
291-
protected val TRANS_LEN = 1 // eval: 1
292-
protected val BLOCK_TRANS = false.B
293-
294-
// inst data
287+
protected val ALIGNED_INST_WIDTH = log2Ceil(AxiInstDataWidth / 8)
288+
protected val OFFSET_INST_WIDTH = log2Ceil(AxiInstDataWidth)
289+
protected val MASK_INST_WIDTH = AxiInstDataWidth * 2
290+
protected val AXI_INST_SIZE = if (SoCEna) 2.U else 3.U // because the flash only support 4 bytes access
291+
292+
protected val ALIGNED_MEM_WIDTH = log2Ceil(AxiDataWidth / 8)
293+
protected val OFFSET_MEM_WIDTH = log2Ceil(AxiDataWidth)
294+
protected val MASK_MEM_WIDTH = AxiDataWidth * 2
295+
296+
protected val TRANS_LEN = 1 // eval: 1
297+
protected val BLOCK_TRANS = false.B
298+
299+
// ================================inst data=======================
295300
// no-aligned visit
296-
protected val instTransAligned = WireDefault(BLOCK_TRANS || io.inst.addr(ALIGNED_WIDTH - 1, 0) === 0.U)
301+
protected val instTransAligned = WireDefault(BLOCK_TRANS || io.inst.addr(ALIGNED_INST_WIDTH - 1, 0) === 0.U)
297302
protected val instSizeByte = WireDefault(io.inst.size === AXI4Bridge.SIZE_B)
298303
protected val instSizeHalf = WireDefault(io.inst.size === AXI4Bridge.SIZE_H)
299304
protected val instSizeWord = WireDefault(io.inst.size === AXI4Bridge.SIZE_W)
300305
protected val instSizeDouble = WireDefault(io.inst.size === AXI4Bridge.SIZE_D)
301-
// opa: 0100xxx
306+
// opa: 0xxx
302307
// opb: b: 0000
303308
// h: 0001
304309
// w: 0011
305310
// d: 0111
306-
protected val instAddrOpA = WireDefault(UInt(4.W), Cat(0.U, io.inst.addr(ALIGNED_WIDTH - 1, 0)))
311+
protected val instAddrOpA = WireDefault(UInt(4.W), Cat(0.U, io.inst.addr(ALIGNED_INST_WIDTH - 1, 0)))
307312
protected val instAddrOpB = WireDefault(
308313
UInt(4.W),
309314
(Fill(4, instSizeByte) & "b0000".U(4.W))
@@ -313,26 +318,26 @@ class AXI4Bridge() extends Module with AXI4Config with InstConfig {
313318
)
314319

315320
protected val instAddrEnd = WireDefault(UInt(4.W), instAddrOpA + instAddrOpB)
316-
protected val instOverstep = WireDefault(instAddrEnd(3, ALIGNED_WIDTH) =/= 0.U)
321+
protected val instOverstep = WireDefault(instAddrEnd(3, ALIGNED_INST_WIDTH) =/= 0.U)
317322

318323
instAxiLen := Mux(instTransAligned.asBool(), (TRANS_LEN - 1).U, Cat(Fill(7, "b0".U(1.W)), instOverstep))
319324
protected val instAxiSize = AXI_INST_SIZE
320-
protected val instAxiAddr = if (SoCEna) io.inst.addr else Cat(io.inst.addr(AxiAddrWidth - 1, ALIGNED_WIDTH), Fill(ALIGNED_WIDTH, "b0".U(1.W)))
321-
protected val instAlignedOffsetLow = Wire(UInt(OFFSET_WIDTH.W))
322-
protected val instAlignedOffsetHig = Wire(UInt(OFFSET_WIDTH.W))
323-
protected val instMask = Wire(UInt(MASK_WIDTH.W))
325+
protected val instAxiAddr = Cat(io.inst.addr(AxiAddrWidth - 1, ALIGNED_INST_WIDTH), Fill(ALIGNED_INST_WIDTH, "b0".U(1.W)))
326+
protected val instAlignedOffsetLow = Wire(UInt(OFFSET_INST_WIDTH.W))
327+
protected val instAlignedOffsetHig = Wire(UInt(OFFSET_INST_WIDTH.W))
328+
protected val instMask = Wire(UInt(MASK_INST_WIDTH.W))
324329

325-
instAlignedOffsetLow := Cat(OFFSET_WIDTH.U - Fill(ALIGNED_WIDTH, "b0".U(1.W)), io.inst.addr(ALIGNED_WIDTH - 1, 0)) << 3
330+
instAlignedOffsetLow := Cat(OFFSET_INST_WIDTH.U - Fill(ALIGNED_INST_WIDTH, "b0".U(1.W)), io.inst.addr(ALIGNED_INST_WIDTH - 1, 0)) << 3
326331
instAlignedOffsetHig := BusWidth.U - instAlignedOffsetLow
327332
instMask := (
328-
(Fill(MASK_WIDTH, instSizeByte) & Cat(Fill(8, "b0".U(1.W)), "hff".U(8.W)))
329-
| (Fill(MASK_WIDTH, instSizeHalf) & Cat(Fill(16, "b0".U(1.W)), "hffff".U(16.W)))
330-
| (Fill(MASK_WIDTH, instSizeWord) & Cat(Fill(32, "b0".U(1.W)), "hffffffff".U(32.W)))
331-
| (Fill(MASK_WIDTH, instSizeDouble) & Cat(Fill(64, "b0".U(1.W)), "hffffffff_ffffffff".U(64.W)))
333+
(Fill(MASK_INST_WIDTH, instSizeByte) & Cat(Fill(8, "b0".U(1.W)), "hff".U(8.W)))
334+
| (Fill(MASK_INST_WIDTH, instSizeHalf) & Cat(Fill(16, "b0".U(1.W)), "hffff".U(16.W)))
335+
| (Fill(MASK_INST_WIDTH, instSizeWord) & Cat(Fill(32, "b0".U(1.W)), "hffffffff".U(32.W)))
336+
| (Fill(MASK_INST_WIDTH, instSizeDouble) & Cat(Fill(64, "b0".U(1.W)), "hffffffff_ffffffff".U(64.W)))
332337
) << instAlignedOffsetLow
333338

334-
protected val instMaskLow = instMask(AxiDataWidth - 1, 0)
335-
protected val instMaskHig = instMask(MASK_WIDTH - 1, AxiDataWidth)
339+
protected val instMaskLow = instMask(AxiInstDataWidth - 1, 0)
340+
protected val instMaskHig = instMask(MASK_INST_WIDTH - 1, AxiInstDataWidth)
336341
protected val instAxiUser = WireDefault(UInt(AxiUserLen.W), Fill(AxiUserLen, "b0".U(1.W)))
337342
protected val instReady = RegInit(false.B)
338343
protected val instReadyNxt = WireDefault(instTransDone)
@@ -352,14 +357,14 @@ class AXI4Bridge() extends Module with AXI4Config with InstConfig {
352357
}
353358
io.inst.resp := instResp
354359

355-
// ================================mem data
356-
protected val memTransAligned = WireDefault(BLOCK_TRANS || io.mem.addr(ALIGNED_WIDTH - 1, 0) === 0.U)
360+
// ================================mem data=======================
361+
protected val memTransAligned = WireDefault(BLOCK_TRANS || io.mem.addr(ALIGNED_MEM_WIDTH - 1, 0) === 0.U)
357362
protected val memSizeByte = WireDefault(io.mem.size === AXI4Bridge.SIZE_B)
358363
protected val memSizeHalf = WireDefault(io.mem.size === AXI4Bridge.SIZE_H)
359364
protected val memSizeWord = WireDefault(io.mem.size === AXI4Bridge.SIZE_W)
360365
protected val memSizeDouble = WireDefault(io.mem.size === AXI4Bridge.SIZE_D)
361366

362-
protected val memAddrOpA = WireDefault(UInt(4.W), Cat(0.U, io.mem.addr(ALIGNED_WIDTH - 1, 0)))
367+
protected val memAddrOpA = WireDefault(UInt(4.W), Cat(0.U, io.mem.addr(ALIGNED_MEM_WIDTH - 1, 0)))
363368
protected val memAddrOpB = WireDefault(
364369
UInt(4.W),
365370
(Fill(4, memSizeByte) & "b0000".U(4.W))
@@ -369,7 +374,7 @@ class AXI4Bridge() extends Module with AXI4Config with InstConfig {
369374
)
370375

371376
protected val memAddrEnd = WireDefault(UInt(4.W), memAddrOpA + memAddrOpB)
372-
protected val memOverstep = WireDefault(memAddrEnd(3, ALIGNED_WIDTH) =/= 0.U)
377+
protected val memOverstep = WireDefault(memAddrEnd(3, ALIGNED_MEM_WIDTH) =/= 0.U)
373378

374379
memAxiLen := Mux(memTransAligned.asBool(), (TRANS_LEN - 1).U, Cat(Fill(7, "b0".U(1.W)), memOverstep))
375380

@@ -387,22 +392,22 @@ class AXI4Bridge() extends Module with AXI4Config with InstConfig {
387392
memAxiSize := 3.U
388393
}
389394

390-
protected val memAxiAddr = Cat(io.mem.addr(AxiAddrWidth - 1, ALIGNED_WIDTH), Fill(ALIGNED_WIDTH, "b0".U(1.W)))
391-
protected val memAlignedOffsetLow = Wire(UInt(OFFSET_WIDTH.W))
392-
protected val memAlignedOffsetHig = Wire(UInt(OFFSET_WIDTH.W))
393-
protected val memMask = Wire(UInt(MASK_WIDTH.W))
395+
protected val memAxiAddr = Cat(io.mem.addr(AxiAddrWidth - 1, ALIGNED_MEM_WIDTH), Fill(ALIGNED_MEM_WIDTH, "b0".U(1.W)))
396+
protected val memAlignedOffsetLow = Wire(UInt(OFFSET_MEM_WIDTH.W))
397+
protected val memAlignedOffsetHig = Wire(UInt(OFFSET_MEM_WIDTH.W))
398+
protected val memMask = Wire(UInt(MASK_MEM_WIDTH.W))
394399

395-
memAlignedOffsetLow := Cat(OFFSET_WIDTH.U - Fill(ALIGNED_WIDTH, "b0".U(1.W)), io.mem.addr(ALIGNED_WIDTH - 1, 0)) << 3
400+
memAlignedOffsetLow := Cat(OFFSET_MEM_WIDTH.U - Fill(ALIGNED_MEM_WIDTH, "b0".U(1.W)), io.mem.addr(ALIGNED_MEM_WIDTH - 1, 0)) << 3
396401
memAlignedOffsetHig := BusWidth.U - memAlignedOffsetLow
397402
memMask := (
398-
(Fill(MASK_WIDTH, memSizeByte) & Cat(Fill(8, "b0".U(1.W)), "hff".U(8.W)))
399-
| (Fill(MASK_WIDTH, memSizeHalf) & Cat(Fill(16, "b0".U(1.W)), "hffff".U(16.W)))
400-
| (Fill(MASK_WIDTH, memSizeWord) & Cat(Fill(32, "b0".U(1.W)), "hffffffff".U(32.W)))
401-
| (Fill(MASK_WIDTH, memSizeDouble) & Cat(Fill(64, "b0".U(1.W)), "hffffffff_ffffffff".U(64.W)))
403+
(Fill(MASK_MEM_WIDTH, memSizeByte) & Cat(Fill(8, "b0".U(1.W)), "hff".U(8.W)))
404+
| (Fill(MASK_MEM_WIDTH, memSizeHalf) & Cat(Fill(16, "b0".U(1.W)), "hffff".U(16.W)))
405+
| (Fill(MASK_MEM_WIDTH, memSizeWord) & Cat(Fill(32, "b0".U(1.W)), "hffffffff".U(32.W)))
406+
| (Fill(MASK_MEM_WIDTH, memSizeDouble) & Cat(Fill(64, "b0".U(1.W)), "hffffffff_ffffffff".U(64.W)))
402407
) << memAlignedOffsetLow
403408

404409
protected val memMaskLow = memMask(AxiDataWidth - 1, 0)
405-
protected val memMaskHig = memMask(MASK_WIDTH - 1, AxiDataWidth)
410+
protected val memMaskHig = memMask(MASK_MEM_WIDTH - 1, AxiDataWidth)
406411
protected val memStrb = Wire(UInt((AxiDataWidth / 8).W))
407412

408413
memStrb := (
@@ -412,8 +417,8 @@ class AXI4Bridge() extends Module with AXI4Config with InstConfig {
412417
| ((Fill(8, memSizeDouble) & "b1111_1111".U(8.W)))
413418
)
414419

415-
protected val memStrbLow = WireDefault(UInt((AxiDataWidth / 8).W), memStrb << io.mem.addr(ALIGNED_WIDTH - 1, 0))
416-
protected val memStrbHig = WireDefault(UInt((AxiDataWidth / 8).W), memStrb >> ((AxiDataWidth / 8).U - io.mem.addr(ALIGNED_WIDTH - 1, 0)))
420+
protected val memStrbLow = WireDefault(UInt((AxiDataWidth / 8).W), memStrb << io.mem.addr(ALIGNED_MEM_WIDTH - 1, 0))
421+
protected val memStrbHig = WireDefault(UInt((AxiDataWidth / 8).W), memStrb >> ((AxiDataWidth / 8).U - io.mem.addr(ALIGNED_MEM_WIDTH - 1, 0)))
417422

418423
protected val memAxiUser = Fill(AxiUserLen, "b0".U(1.W))
419424
protected val memReady = RegInit(false.B)

‎rtl/tc_l2/src/main/scala/axi4/AXI4SigBridge.scala‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
// import chisel3.util._
55
// import AXI4Bridge._
66

7-
// class AXI4SigBridge extends Module with AXI4Config with InstConfig {
7+
// class AXI4SigBridge extends Module with AXI4Config {
88
// val io = IO(new Bundle {
99
// val rw: AXI4USERIO = new AXI4USERIO
1010
// val axi: AXI4IO = new AXI4IO

0 commit comments

Comments
 (0)