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Copy file name to clipboardExpand all lines: dspic33e-adc-fir-dma/README.md
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## Description:
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In this example, ADC is configured to sample (AN5) at 250 KHz rate and the converted data is assembled in a 480-sample buffer. This input data is then filtered using the block FIR filter function from the DSP library. A 20-tap filter is used.
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Timer 3 is setup to time-out every 4 microseconds (250 KHz rate). On every Timer3 time-out (every Ts = 4 microsecs), the ADC module will stop sampling and trigger a 10-bit A/D conversion. At that time, the conversion process starts and completes Tc = 12 * Tad = 1.2 microsecs later.
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When the conversion is complete, the module starts sampling again.
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However, since Timer3 is already on and counting, about (Ts-Tc) secs later Timer3 will expire again and trigger the next conversion.
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The DMA is configured in continuous, ping pong mode, such that after the DMA channel has read 480 samples into a buffer (BufferA/BufferB) a DMA interrupt is generated.
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These samples are filtered by a function call in the main function while the DMA controller starts filling new ADC samples into buffer (BufferB/BufferA). Thus the two buffers are alternately filled and processed in an infinite loop.
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The ADC module clock time period is configured as Tad = Tcy * (ADCS+1) = (1/40M) * 1 = 100ns nanosecs with ADCS = 3. Hence the conversion time for 10-bit A/D is 12 * Tad = 1.2 microsecs.
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FIRStruct describes the data structure for FIR filter with the filter specifications given below. FIRStructInit() initializes the FIR filter structure parameters.
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FIRDelayInit() initializes the delay values in the FIR filter structure to zeros. The FIR() function applies an FIR filter to a sequence of source samples and places the result in a sequence of destination samples.
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FIR filter specifications used:
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Sampling freq = 250 KHz
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FIR block size, N = 480
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Number of FIR coefficients, M = 20
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FCY = 40 MIPS
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Passband Frequency = 1300 Hz
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Stopband Frequency = 1350 Hz
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Passband Ripple = 1 dB
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Stopband Ripple = 3 dB
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In this example, ADC is configured to sample (AN5) at 250 KHz rate and the converted data is assembled in a 480-sample buffer. This input data is then filtered using the block FIR filter function from the DSP library. A 20-tap filter is used.
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Timer 3 is setup to time-out every 4 microseconds (250 KHz rate). On every Timer3 time-out (every Ts = 4 microsecs), the ADC module will stop sampling and trigger a 10-bit A/D conversion. At that time, the conversion process starts and completes Tc = 12 * Tad = 1.2 microsecs later.
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When the conversion is complete, the module starts sampling again.
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However, since Timer3 is already on and counting, about (Ts-Tc) secs later Timer3 will expire again and trigger the next conversion.
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The DMA is configured in continuous, ping pong mode, such that after the DMA channel has read 480 samples into a buffer (BufferA/BufferB) a DMA interrupt is generated.
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These samples are filtered by a function call in the main function while the DMA controller starts filling new ADC samples into buffer (BufferB/BufferA). Thus the two buffers are alternately filled and processed in an infinite loop.
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The ADC module clock time period is configured as Tad = Tcy * (ADCS+1) = (1/40M) * 1 = 100ns nanosecs with ADCS = 3. Hence the conversion time for 10-bit A/D is 12 * Tad = 1.2 microsecs.
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FIRStruct describes the data structure for FIR filter with the filter specifications given below. FIRStructInit() initializes the FIR filter structure parameters.
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FIRDelayInit() initializes the delay values in the FIR filter structure to zeros. The FIR() function applies an FIR filter to a sequence of source samples and places the result in a sequence of destination samples.
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FIR filter specifications used:
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Sampling freq = 250 KHz
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FIR block size, N = 480
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Number of FIR coefficients, M = 20
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FCY = 40 MIPS
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Passband Frequency = 1300 Hz
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Stopband Frequency = 1350 Hz
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Passband Ripple = 1 dB
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Stopband Ripple = 3 dB
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Kaiser Windowing
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The FIR() function takes [53+N(4+M)] instruction cycles. In this example, since N = 480 and M = 20, the total number of instruction cycles taken by FIR() is C = 11,573. Since the instruction cycle frequency is FCY = 40 MIPS the total time taken by the FIR filter to filter 480 samples is TFIR = C/FCY = 0.3 millisecs.
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NOTE: A NOP associated with Y memory errata was removed from the fir.s source in the DSP library before using it in this code example, as this errata item only applies to certain dsPIC30F devices and does not affect the dsPIC33E device family.
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void initTmr3();
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void initTmr3();
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Timer 3 is configured to time-out at 250 KHz rate.
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void initAdc1(void);
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void initAdc1(void);
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ADC module is set-up to convert AIN5 input using CH0 S/H on Timer 3 event in 10-bit mode.
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void initDma0(void);
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void initDma0(void);
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DMA channel 0 is confiured in ping-pong mode to move the converted data from ADC to DMA RAM on every sample/convert sequence.
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It generates interrupt after every 480 sample transfer.
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In this example, ADC is configured to sample (AIN5) at 8Khz rate and converted data is assembled as 256 sample buffer before triggering filtering operation.
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Timer 3 is setup to time-out every 125 microseconds (8Khz Rate).
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As a result, the module will stop sampling and trigger a 12-bit A/D conversion on every Timer3 time-out, i.e., Ts=125us.
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At that time, the conversion process starts and completes Tc=14*Tad periods later.
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Timer 3 is setup to time-out every 125 microseconds (8Khz Rate).
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As a result, the module will stop sampling and trigger a 12-bit A/D conversion on every Timer3 time-out, i.e., Ts=125us.
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At that time, the conversion process starts and completes Tc=14*Tad periods later.
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When the conversion completes, the module starts sampling again. However, since Timer3
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is already on and counting, about (Ts-Tc)us later, Timer3 will expire again and trigger
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next conversion.
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ADC module clock time period is configured as Tad=Tcy*(ADCS+1)= (1/40M)*64 = 1.6us (625Khz).
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Hence the conversion time for 12-bit A/D Conversion Time Tc=14*Tad = 22.4us
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void initTmr3();
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void initTmr3();
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Timer 3 is configured to time-out at 8Khz rate.
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void initAdc1(void);
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void initAdc1(void);
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ADC module is set-up to convert AIN5 input using CH0 S/H on Timer 3 event in 12-bit mode.
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void initDma0(void);
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void initDma0(void);
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DMA channel 0 is configured in ping-pong mode to move the converted data from ADC to DMA RAM on every sample/convert sequence.
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It generates interrupt after every 256 sample transfer.
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