Updated review comments

Author: jasminefrancisca

dspic33e-adc-1msps/README.md

@@ -8,15 +8,15 @@ In this example, ADC is set up to convert AIN0 using CH0 and CH1 sample/hold in
 at 1.1MHz throughput rate. ADC clock is configured at 13.3Mhz or Tad=75ns
 ADC Conversion Time for 10-bit conversion is Tc=12 * Tab =  900ns (1.1MHz).
 
-void initAdc1(void);<br />
+void initAdc1(void);  
 ADC CH0 and CH1 S/H is set-up to covert AIN0 in 10-bit mode. ADC is configured to next sample data immediately after the conversion.
 So, ADC keeps conversion data through CH0/CH1 S/H alternatively. Effective conversion rate is 1.1Mhz
 
-void initDma0(void);<br />
+void initDma0(void);  
 DMA channel 0 is configured in ping-pong mode to move the converted data from ADC to DMA RAM on every sample/convert sequence. 
 It generates interrupt after every 16 sample transfer. 
 
-void \_\_attribute\_\_((\_\_interrupt\_\_)) _DMA0Interrupt(void);<br />
+void \_\_attribute\_\_((\_\_interrupt\_\_)) _DMA0Interrupt(void);  
 DMA interrupt service routine, moves the data from DMA buffer to ADC signal buffer and collects 256 samples.
 
 The Toggle frequency of one pulse should be around 240us(micro second), if the operating clock frequency at 40Mhz.

dspic33e-adc-fir-dma/README.md

@@ -4,43 +4,43 @@
 
 ## Description:
 
-In this example, ADC is configured to sample (AN5) at 250 KHz rate and the converted data is assembled in a 480-sample buffer. This input data is then filtered using the block FIR filter function from the DSP library. A 20-tap filter is used.<br />
-Timer 3 is setup to time-out every 4 microseconds (250 KHz rate). On every Timer3 time-out (every Ts = 4 microsecs), the ADC module will stop sampling and trigger a 10-bit A/D conversion. At that time, the conversion process starts and completes Tc = 12 * Tad = 1.2 microsecs later. <br />
-When the conversion is complete, the module starts sampling again. <br />
-However, since Timer3 is already on and counting, about (Ts-Tc) secs later Timer3 will expire again and trigger the next conversion. <br />
-The DMA is configured in continuous, ping pong mode, such that after the DMA channel has read 480 samples into a buffer (BufferA/BufferB) a DMA interrupt is generated.<br /> 
-These samples are filtered by a function call in the main function while the DMA controller starts filling new ADC samples into buffer (BufferB/BufferA). Thus the two buffers are alternately filled and processed in an infinite loop.<br />
-The ADC module clock time period is configured as Tad = Tcy * (ADCS+1) = (1/40M) * 1 = 100ns nanosecs with ADCS = 3. Hence the conversion time for 10-bit A/D is 12 * Tad = 1.2 microsecs.<br />
-FIRStruct describes the data structure for FIR filter with the filter specifications given below. FIRStructInit() initializes the FIR filter structure parameters. <br />
-FIRDelayInit() initializes the delay values in the FIR filter structure to zeros. The FIR() function applies an FIR filter to a sequence of source samples and places the result in a sequence of destination samples.<br />
-
-FIR filter specifications used:<br />
-Sampling freq = 250 KHz<br />
-FIR block size, N = 480<br />
-Number of FIR coefficients, M = 20<br />
-FCY = 40 MIPS<br />
-Passband Frequency = 1300 Hz<br />
-Stopband Frequency = 1350 Hz<br />
-Passband Ripple = 1 dB<br />
-Stopband Ripple = 3 dB<br />
+In this example, ADC is configured to sample (AN5) at 250 KHz rate and the converted data is assembled in a 480-sample buffer. This input data is then filtered using the block FIR filter function from the DSP library. A 20-tap filter is used.  
+Timer 3 is setup to time-out every 4 microseconds (250 KHz rate). On every Timer3 time-out (every Ts = 4 microsecs), the ADC module will stop sampling and trigger a 10-bit A/D conversion. At that time, the conversion process starts and completes Tc = 12 * Tad = 1.2 microsecs later.   
+When the conversion is complete, the module starts sampling again.   
+However, since Timer3 is already on and counting, about (Ts-Tc) secs later Timer3 will expire again and trigger the next conversion.   
+The DMA is configured in continuous, ping pong mode, such that after the DMA channel has read 480 samples into a buffer (BufferA/BufferB) a DMA interrupt is generated.   
+These samples are filtered by a function call in the main function while the DMA controller starts filling new ADC samples into buffer (BufferB/BufferA). Thus the two buffers are alternately filled and processed in an infinite loop.  
+The ADC module clock time period is configured as Tad = Tcy * (ADCS+1) = (1/40M) * 1 = 100ns nanosecs with ADCS = 3. Hence the conversion time for 10-bit A/D is 12 * Tad = 1.2 microsecs.  
+FIRStruct describes the data structure for FIR filter with the filter specifications given below. FIRStructInit() initializes the FIR filter structure parameters.   
+FIRDelayInit() initializes the delay values in the FIR filter structure to zeros. The FIR() function applies an FIR filter to a sequence of source samples and places the result in a sequence of destination samples.  
+
+FIR filter specifications used:  
+Sampling freq = 250 KHz  
+FIR block size, N = 480  
+Number of FIR coefficients, M = 20  
+FCY = 40 MIPS  
+Passband Frequency = 1300 Hz  
+Stopband Frequency = 1350 Hz  
+Passband Ripple = 1 dB  
+Stopband Ripple = 3 dB  
 Kaiser Windowing
 
 The FIR() function takes [53+N(4+M)] instruction cycles. In this example, since N = 480 and M = 20, the total number of instruction cycles taken by FIR() is C = 11,573. Since the instruction cycle frequency is FCY = 40 MIPS the total time taken by the FIR filter to filter 480 samples is TFIR = C/FCY = 0.3 millisecs.
 
 NOTE: A NOP associated with Y memory errata was removed from the fir.s source in the DSP library before using it in this code example, as this errata item only applies to certain dsPIC30F devices and does not affect the dsPIC33E device family.
 
 
-void initTmr3();<br />
+void initTmr3();  
 Timer 3 is configured to time-out at 250 KHz rate. 
 
-void initAdc1(void);<br />
+void initAdc1(void);  
 ADC module is set-up to convert AIN5 input using CH0 S/H on Timer 3 event in 10-bit mode.
 
-void initDma0(void);<br />
+void initDma0(void);  
 DMA channel 0 is confiured in ping-pong mode to move the converted data from ADC to DMA RAM on every sample/convert sequence. 
 It generates interrupt after every 480 sample transfer. 
 
-void \_\_attribute\_\_((\_\_interrupt\_\_)) _DMA0Interrupt(void);<br />
+void \_\_attribute\_\_((\_\_interrupt\_\_)) _DMA0Interrupt(void);  
 DMA interrupt service routine sets flag for FIR filtering on the data buffer.
 
 

dspic33e-adc-iir-filter/README.md

@@ -6,27 +6,27 @@
 
 In this example, ADC is configured to sample (AIN5) at 8Khz rate and converted data is assembled as 256 sample buffer before triggering filtering operation.
 
-Timer 3 is setup to time-out every 125 microseconds (8Khz Rate). <br />
-As a result, the module will stop sampling and trigger a 12-bit A/D conversion on every Timer3 time-out, i.e., Ts=125us. <br />
-At that time, the conversion process starts and completes Tc=14*Tad periods later.<br />
+Timer 3 is setup to time-out every 125 microseconds (8Khz Rate).   
+As a result, the module will stop sampling and trigger a 12-bit A/D conversion on every Timer3 time-out, i.e., Ts=125us.   
+At that time, the conversion process starts and completes Tc=14*Tad periods later.  
 When the conversion completes, the module starts sampling again. However, since Timer3 
 is already on and counting, about (Ts-Tc)us later, Timer3 will expire again and trigger 
 next conversion. 
 
 ADC module clock time period is configured as Tad=Tcy*(ADCS+1)= (1/40M)*64 = 1.6us (625Khz). 
 Hence the conversion time for 12-bit A/D Conversion Time Tc=14*Tad = 22.4us
 
-void initTmr3();<br />
+void initTmr3();  
 Timer 3 is configured to time-out at 8Khz rate. 
 
-void initAdc1(void);<br />
+void initAdc1(void);  
 ADC module is set-up to convert AIN5 input using CH0 S/H on Timer 3 event in 12-bit mode.
 
-void initDma0(void);<br />
+void initDma0(void);  
 DMA channel 0 is configured in ping-pong mode to move the converted data from ADC to DMA RAM on every sample/convert sequence. 
 It generates interrupt after every 256 sample transfer. 
 
-void \_\_attribute\_\_((\_\_interrupt\_\_)) _DMA0Interrupt(void);<br />
+void \_\_attribute\_\_((\_\_interrupt\_\_)) _DMA0Interrupt(void);  
 DMA interrupt service routine performs IIR filtering on the data buffer.
 
 

dspic33e-pmp/README.md

@@ -12,16 +12,16 @@ The PMP module is configured in the Master Mode.
 Set the I/O ports as digital ports.
 
 
-mLDCInit()<br />
+mLDCInit()  
 This function will initialise the LCDinit pointer to sets LCDState mchine to _uLCDstate = 2
 
 
-TimerInit()<br />
+TimerInit()  
 This function will enable to run the Timer
 
 
-BannerStart()<br />
-This function will enable to Setup the banner processing<br />
+BannerStart()  
+This function will enable to Setup the banner processing  
 The following events are performed in this function
 -  Check if the LCD is busy
 -  Set the Cursor to the starting point
@@ -30,22 +30,22 @@ The following events are performed in this function
 
 In the While loop the following events follow.
 
-LCDProcessEvents()<br />
+LCDProcessEvents()  
 This is a state machine to issue commands and data to LCD. Must be called periodically to make LCD message processing.
 The communication with the LCD module is enabled through the PMP module.
 This function Initialises the LCD function + Processes a series of LCD events.
 
--  Initialises the LCD function.<br />
+-  Initialises the LCD function.  
    Open the PMP module for communication with LCD ( Case2) 
    complete a set of events to initialise the LCD from (Case 64 to case 71)
    Clear the LCD state machine i.e (_uLCDstate = 0)
 
 
-TimerIsOverflowEvent()<br />
+TimerIsOverflowEvent()  
 Only on timer Overflow the BannerProcessEvents is processed
 
 
-BannerProcessEvents()<br />
+BannerProcessEvents()  
 -  Display the Banner array 
    Pick the character to be displayed from the banner pointer
    Prepare the character for display

dspic33e-pwm-oc-ptg/README.md

@@ -17,9 +17,9 @@ phase shift of half the PWM period between OC1 and OC2 outputs.
 
 PTG Timer is configured for delay of 20us and calculation is as follows:
 
-Required delay: 20us<br/>
-PTG Clock: 70MHz<br/>
-COunt in PTGT0LIm: 20us/(1/70MHz) = 20us*70Mhz = 1400;<br/>
+Required delay: 20us  
+PTG Clock: 70MHz  
+COunt in PTGT0LIm: 20us/(1/70MHz) = 20us*70Mhz = 1400;  
 
 In this example OC2 is configured for 25% duty cycle or 10us .
 

dspic33e-spi-loopback/README.md

@@ -7,29 +7,29 @@
 In this code examples, 2x16=32words is transmitted using SPI and received back in ping-pong mode. 
 This operation happens continuously.
 
-Note: RG7 pin should be connected to RG8 externally (Depending on the PIN mapping, accordingly the it varies.Pls refer corresponding PIM sheet respectively)<br/>
-For dspic33ep512mu810 :RG7 pin should be connected to RG8 externally .<br/>
-For dspic33ep256gp506 :RF7 pin should be connected to RF8 externally .<br/>
-For dspic33ep512gm710 :RF7 pin should be connected to RF8 externally .<br/>
+Note: RG7 pin should be connected to RG8 externally (Depending on the PIN mapping, accordingly the it varies.Pls refer corresponding PIM sheet respectively)  
+For dspic33ep512mu810 :RG7 pin should be connected to RG8 externally .  
+For dspic33ep256gp506 :RF7 pin should be connected to RF8 externally .  
+For dspic33ep512gm710 :RF7 pin should be connected to RF8 externally .  
 
-void CfgSpi1Master(void)/void CfgSpi2Master(void)<br/>
+void CfgSpi1Master(void)/void CfgSpi2Master(void)  
 This function configures SPI in master mode to transmit/receive 16-bit word.
 
-void initSPIBuff(void)<br/>
+void initSPIBuff(void)  
 This function pre-initialise the transmit data buffer and DMA RAM buffer for transmission
 
-void cfgDma0SpiTx(void)<br/>
+void cfgDma0SpiTx(void)  
 This function configures DMA channel 0 for SPI transmission. DMA is configured in ping-pong mode 
 with auto increment addressing for DMA memory read.
 
-void cfgDma1SpiRx(void)<br/>
+void cfgDma1SpiRx(void)  
 This function configures DMA channel 0 for SPI reception. DMA is configured in ping-pong mode 
 with auto increment addressing for DMA memory write.
 
-void \_\_attribute\_\_((\_\_interrupt\_\_)) _DMA0Interrupt(void)<br/>
+void \_\_attribute\_\_((\_\_interrupt\_\_)) _DMA0Interrupt(void)  
 This interrupt routine handles transmit DMA interrupt
 
-void \_\_attribute\_\_((\_\_interrupt\_\_)) _DMA1Interrupt(void)<br/>
+void \_\_attribute\_\_((\_\_interrupt\_\_)) _DMA1Interrupt(void)  
 This interrupt routine handles the receive ping-pong buffer.
 
 

dspic33e-spi-no-dma/README.md

@@ -12,9 +12,9 @@ The code sends from 00h through FFh and then cycles through again.  A delay was
 
 Externally Connect for testing:
 -------------------------------
-RF7 & RF8 on Expl16 board for dspic33ep256GP506 PIM<br/>
-RF7 & RF8 on Expl16 board for dspic33ep512gm710 PIM<br/>
-RF2 & RF3 on Expl16 board for dspic33ep512mu810 PIM<br/>
+RF7 & RF8 on Expl16 board for dspic33ep256GP506 PIM  
+RF7 & RF8 on Expl16 board for dspic33ep512gm710 PIM  
+RF2 & RF3 on Expl16 board for dspic33ep512mu810 PIM  
 
 
 ## Hardware Used

dspic33e-timer1-rtc/README.md

@@ -9,7 +9,7 @@ timers. Of these, the Timer1 module has the capability to be clocked by
 an external asynchronous 32KHz crystal connected to the device via the
 SOSCI and SOSCO pins. The attached code example demonstrates how Timer1
 may be configured to use the 32KHz secondary oscillator for a real-time
-clock (RTC) application.<br/><br/>
+clock (RTC) application.    
 Configuring Timer1 for the real-time clock application is a two-step
 process. In the first step, the code demonstrates how the secondary
 oscillator may be enabled via a special write sequence to the OSCCON