Skip to content

Commit b0a8492

Browse files
ArcEyeArcEye
authored
Update board config (#110)
Update board config
2 parents 7c8c7d2 + f96642c commit b0a8492

File tree

2 files changed

+238
-0
lines changed

2 files changed

+238
-0
lines changed

‎HW/hm2/config/DExx_Nano_xxx_Cramps/PIN_st_fpga_soc_dc1G.vhd‎

Lines changed: 200 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,200 @@
1+
library IEEE;
2+
use IEEE.std_logic_1164.all; -- defines std_logic types
3+
use IEEE.STD_LOGIC_ARITH.ALL;
4+
use IEEE.STD_LOGIC_UNSIGNED.ALL;
5+
6+
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
7+
-- http://www.mesanet.com
8+
--
9+
-- This program is is licensed under a disjunctive dual license giving you
10+
-- the choice of one of the two following sets of free software/open source
11+
-- licensing terms:
12+
--
13+
-- * GNU General Public License (GPL), version 2.0 or later
14+
-- * 3-clause BSD License
15+
--
16+
--
17+
-- The GNU GPL License:
18+
--
19+
-- This program is free software; you can redistribute it and/or modify
20+
-- it under the terms of the GNU General Public License as published by
21+
-- the Free Software Foundation; either version 2 of the License, or
22+
-- (at your option) any later version.
23+
--
24+
-- This program is distributed in the hope that it will be useful,
25+
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
26+
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27+
-- GNU General Public License for more details.
28+
--
29+
-- You should have received a copy of the GNU General Public License
30+
-- along with this program; if not, write to the Free Software
31+
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
32+
--
33+
--
34+
-- The 3-clause BSD License:
35+
--
36+
-- Redistribution and use in source and binary forms, with or without
37+
-- modification, are permitted provided that the following conditions
38+
-- are met:
39+
--
40+
-- * Redistributions of source code must retain the above copyright
41+
-- notice, this list of conditions and the following disclaimer.
42+
--
43+
-- * Redistributions in binary form must reproduce the above
44+
-- copyright notice, this list of conditions and the following
45+
-- disclaimer in the documentation and/or other materials
46+
-- provided with the distribution.
47+
--
48+
-- * Neither the name of Mesa Electronics nor the names of its
49+
-- contributors may be used to endorse or promote products
50+
-- derived from this software without specific prior written
51+
-- permission.
52+
--
53+
--
54+
-- Disclaimer:
55+
--
56+
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
57+
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
58+
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
59+
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
60+
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
61+
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
62+
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
63+
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
64+
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
65+
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
66+
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
67+
-- POSSIBILITY OF SUCH DAMAGE.
68+
--
69+
70+
use work.IDROMConst.all;
71+
72+
package Pintypes is
73+
constant ModuleID : ModuleIDType :=(
74+
-- GTag Version Clock NumInst BaseAddr NumRegisters Strides MultiRegs
75+
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
76+
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
77+
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
78+
(QcountTag, x"02", ClockLowTag, x"06", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
79+
(StepGenTag, x"02", ClockLowTag, x"06", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
80+
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
81+
(PWMTag, x"00", ClockHighTag, x"00", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
82+
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
83+
(NANOADCTag, x"00", ClockLowTag, x"08", NANOADCAddr&PadT, NANOADCNumRegs, x"00", NANOADCBitMask),
84+
(FWIDTag, x"00", ClockLowTag, x"01", FWIDAddr&PadT, FWIDNumRegs, x"00", FWIDMPBitMask),
85+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
86+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
87+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
88+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
89+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
90+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
91+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
92+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
93+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
94+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
95+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
96+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
97+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
98+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
99+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
100+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
101+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
102+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
103+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
104+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
105+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
106+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
107+
);
108+
109+
110+
constant PinDesc : PinDescType :=(
111+
-- Base Sec Sec Sec
112+
-- func unit func pin -- hostmot2 DE0-Nano pin Function
113+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 00 GPIO_0 20 01 GP_Input_10
114+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 01 GPIO_0 20 02 GP_Input_04
115+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 02 GPIO_0 21 03 GP_Input_05
116+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 03 GPIO_0 22 04 GP_Input_00
117+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 04 GPIO_0 23 05 GP_Input_06
118+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 05 GPIO_0 24 06 GP_Input_01
119+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 06 GPIO_0 25 07 GP_Input_11
120+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 07 GPIO_0 26 08 GP_Input_12
121+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 08 GPIO_0 27 09 GP_Input_13
122+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 09 GPIO_0 28 10 GP_Input_14
123+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 10 GPIO_0 29 13 GP_Input_07
124+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 11 GPIO_0 30 14 GP_Input_15
125+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 12 GPIO_0 31 15 GP_Input_09
126+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 13 GPIO_0 32 16 GP_Input_08
127+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 14 GPIO_0 33 17 GP_Input_03
128+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 15 GPIO_0 34 18 GP_Input_02
129+
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 16 GPIO_0 01 19 Enc0 B
130+
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 17 GPIO_0 02 20 Enc0 A
131+
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 18 GPIO_0 03 21 Enc1 A
132+
IOPortTag & x"00" & QCountTag & QCountIdxPin, -- I/O 19 GPIO_0 04 22 Enc0 Z
133+
IOPortTag & x"01" & QCountTag & QCountIdxPin, -- I/O 20 GPIO_0 05 23 Enc1 Z
134+
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 21 GPIO_0 06 24 Enc1 B
135+
IOPortTag & x"02" & QCountTag & QCountQBPin, -- I/O 22 GPIO_0 07 25 Enc2 B
136+
IOPortTag & x"02" & QCountTag & QCountQAPin, -- I/O 23 GPIO_0 08 26 Enc2 A
137+
IOPortTag & x"03" & QCountTag & QCountQAPin, -- I/O 24 GPIO_0 09 27 Enc3 A
138+
IOPortTag & x"02" & QCountTag & QCountIdxPin, -- I/O 25 GPIO_0 10 28 Enc2 Z
139+
IOPortTag & x"03" & QCountTag & QCountIdxPin, -- I/O 26 GPIO_0 11 31 Enc3 Z
140+
IOPortTag & x"03" & QCountTag & QCountQBPin, -- I/O 27 GPIO_0 12 32 Enc3 B
141+
IOPortTag & x"04" & QCountTag & QCountQBPin, -- I/O 28 GPIO_0 13 33 Enc4 B
142+
IOPortTag & x"04" & QCountTag & QCountQAPin, -- I/O 29 GPIO_0 14 34 Enc4 A
143+
IOPortTag & x"05" & QCountTag & QCountQAPin, -- I/O 30 GPIO_0 15 35 Enc5 A
144+
IOPortTag & x"04" & QCountTag & QCountIdxPin, -- I/O 31 GPIO_0 16 36 Enc4 Z
145+
IOPortTag & x"05" & QCountTag & QCountIdxPin, -- I/O 32 GPIO_0 17 37 Enc5 Z
146+
IOPortTag & x"05" & QCountTag & QCountQBPin, -- I/O 33 GPIO_0 18 38 Enc5 B
147+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 34 GPIO_0 35 39 GP_Output_HC_17
148+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 35 GPIO_0 36 40 GP_Output_HC_16
149+
150+
-- Base Sec Sec Sec
151+
-- func unit func pin -- hostmot2 DE0-Nano pin Function
152+
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 36 GPIO_1 01 01 rs_422_Tx_0
153+
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 37 GPIO_1 02 02 rs_422_Rx_0
154+
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 38 GPIO_1 03 03 Step_5
155+
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 39 GPIO_1 04 04 Dir_5
156+
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 40 GPIO_1 05 05 Step_4
157+
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 41 GPIO_1 06 06 Dir_4
158+
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 42 GPIO_1 07 07 Step_3
159+
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 43 GPIO_1 08 08 Dir_3
160+
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 44 GPIO_1 09 09 Step_2
161+
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 45 GPIO_1 10 10 Dir_2
162+
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 46 GPIO_1 11 13 Step_1
163+
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 47 GPIO_1 12 14 Dir_1
164+
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 48 GPIO_1 13 15 Step_0
165+
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 49 GPIO_1 14 16 Dir_0
166+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 50 GPIO_1 15 17 Step4_Enable
167+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 51 GPIO_1 16 18 Step5_Enable
168+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 52 GPIO_1 17 19 Step2_Enable
169+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 53 GPIO_1 18 20 Step3_Enable
170+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 54 GPIO_1 19 21 Step0_Enable
171+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 55 GPIO_1 20 22 Step1_Enable
172+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 56 GPIO_1 21 23 GP_Output_00
173+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 57 GPIO_1 22 24 GP_Output_08
174+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 58 GPIO_1 23 25 GP_Output_01
175+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 59 GPIO_1 24 26 GP_Output_09
176+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 60 GPIO_1 25 27 GP_Output_02
177+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 61 GPIO_1 26 28 GP_Output_10
178+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 62 GPIO_1 27 31 GP_Output_03
179+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 63 GPIO_1 28 32 GP_Output_11
180+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 64 GPIO_1 29 33 GP_Output_04
181+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 65 GPIO_1 30 34 GP_Output_12
182+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 66 GPIO_1 31 35 GP_Output_05
183+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 67 GPIO_1 32 36 GP_Output_13
184+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 68 GPIO_1 33 37 GP_Output_06
185+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 69 GPIO_1 34 38 GP_Output_14
186+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 70 GPIO_1 35 39 GP_Output_07
187+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 71 GPIO_1 36 40 GP_Output_15
188+
189+
-- Remainder of 144 pin descriptors are unused
190+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
191+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
192+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
193+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
194+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
195+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
196+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
197+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
198+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
199+
200+
end package Pintypes; --PIN_Cramps_3x24_dpll_irq

‎HW/hm2/config/DExx_Nano_xxx_Cramps/atlas_st_fpga_soc_dc1G.sv‎

Lines changed: 38 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,38 @@
1+
package boardtype;
2+
// DE0-Nano Dev kit and I/O adaptors specific info
3+
// {STRAIGHT=0,DB25=1} BoardAdaptor;
4+
5+
parameter BoardAdaptor = 0;
6+
parameter ClockHigh = 200000000; // 200 MHz
7+
parameter ClockMed = 100000000; // 100 MHz
8+
parameter ClockLow = 50000000; // 50 MHz
9+
// parameter BoardNameLow = 32'h41524554; // "TERA"
10+
// parameter BoardNameHigh = 32'h4E304544; // "DE0N"
11+
parameter BoardNameLow = 32'h4153454D; // "MESA"
12+
parameter BoardNameHigh = 32'h35324935; // "5I25"
13+
parameter FPGASize = 9; // Reported as 32-bit value in IDROM.vhd (9 matches Mesanet value for 5i25)
14+
// FIXME: Figure out Mesanet encoding and put something sensible here
15+
parameter FPGAPins = 144; // Total Number of available I/O pins for Hostmot2 use Reported as 32-bit value in IDROM.vhd
16+
// Proposal: On DE0 NANO board Limit to total count of gpios + arduinoconnectors + ltc + adc I/Os
17+
// Maximum of 144 pindesc entries currently hard-coded in IDROM.vhd
18+
parameter IOPorts = 3; // Number of external ports (DE0-Nano_DB25 can have 2 on each 40-pin expansion header)
19+
parameter IOWidth = 72; // Number of total I/O pins = IOPorts * PortWidth
20+
parameter PortWidth = 24; // Number of I/O pins per port: 17 per DB25
21+
parameter LIOWidth = 0; // Number of local I/Os (used for on-board serial-port on Mesanet cards)
22+
parameter LEDCount = 0; // Number of LEDs
23+
parameter SepClocks = "true"; // Deprecated
24+
parameter OneWS = "true"; // Deprecated
25+
parameter BusWidth = 32;
26+
parameter AddrWidth = 16;
27+
28+
parameter GPIOWidth = 36;
29+
parameter NumGPIO = 2;
30+
parameter MuxGPIOIOWidth = IOWidth/NumGPIO;
31+
parameter MuxLedWidth = LEDCount/NumGPIO;
32+
parameter ADC = "DE0-Nano-SoC";
33+
parameter Mux_En = 0;
34+
parameter Capsense = 0;
35+
parameter NumSense = 4;
36+
// Capsense Pins: '{.. etc , Sensor1, Sensor0, charge out} // GPIO 0-71
37+
parameter int Capsense_Pins[NumSense:0] = '{ 40, 39, 38, 37, 36 };
38+
endpackage //_HeaderIncluded

0 commit comments

Comments
 (0)