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ArcEyeArcEye
authored
Sserial work (#109)
Sserial work
2 parents fdc9ddc + 94544ac commit 7c8c7d2

22 files changed

+1288
-738
lines changed

‎HW/QuartusProjects/Common/bidir_io.sv‎

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
module bidir_io
2-
#(parameter IOWidth=36, parameter PortNumWidth=8)
2+
#(parameter IOWidth=36, parameter PortNumWidth=8, parameter Mux_En = 1)
33
(
44
input [PortNumWidth-1:0] portselnum [IOWidth-1:0],
55
input clk,
@@ -24,8 +24,14 @@ generate
2424

2525
always @ (posedge clk)
2626
begin
27-
io_data_in[loop] <= gpioport[portselnum[loop]];
28-
outmuxdataout[loop] <= out_data[portselnum[loop]];
27+
if (Mux_En == 1) begin
28+
io_data_in[loop] <= gpioport[portselnum[loop]];
29+
outmuxdataout[loop] <= out_data[portselnum[loop]];
30+
end
31+
else begin
32+
io_data_in[loop] <= gpioport[loop];
33+
outmuxdataout[loop] <= out_data[loop];
34+
end
2935
end
3036
end
3137
endgenerate

‎HW/QuartusProjects/Common/gpio_adr_decoder_reg.sv‎

Lines changed: 127 additions & 111 deletions
Original file line numberDiff line numberDiff line change
@@ -79,7 +79,9 @@ parameter NumGPIO = 2;
7979

8080
parameter Capsense = 1;
8181
parameter NumSense = 4;
82+
parameter int Capsense_Pins[NumSense:0] = '{40, 39, 38, 37, 36};
8283
parameter ADC = "";
84+
parameter Mux_En = 1;
8385
// local param
8486
parameter IoRegWidth = 24;
8587
parameter AdcOutShift = 2;
@@ -147,19 +149,19 @@ parameter TotalNumregs = Mux_regPrIOReg * NumIOAddrReg * NumPinsPrIOAddr;
147149

148150
// Touch sensor:
149151
reg [BusWidth-1:0] hysteresis_reg;
150-
reg [1:0]sr_delay;
152+
reg [1:0] sr_delay;
151153
reg reset_sr;
152-
reg [2:0]sr_init_delay;
154+
reg [2:0] sr_init_delay;
153155
reg reset_init_sr;
154156
wire [NumSense-1:0] sense;
155157
wire charge;
156158
wire [3:0] hysteresis[NumSense-1:0];
157-
158-
wire sr_delay_act;
159-
wire sr_init_delay_act;
160-
wire sense_reset;
159+
160+
wire sr_delay_act;
161+
wire sr_init_delay_act;
162+
wire sense_reset;
161163
// wire sense_reset = ~reset_reg_N;
162-
164+
163165
genvar sh;
164166
generate
165167
for(sh=0;sh<NumSense;sh=sh+1) begin : sense_hystloop
@@ -168,22 +170,22 @@ parameter TotalNumregs = Mux_regPrIOReg * NumIOAddrReg * NumPinsPrIOAddr;
168170
endgenerate
169171

170172

171-
adc_ltc2308_fifo adc_ltc2308_fifo_inst
172-
(
173-
.clock(CLOCK) , // input clock_sig
174-
.reset_n(reset_reg_N) , // input reset_n_sig
175-
.addr(busaddress[2]) , // input addr_sig
176-
.read_outdata(adc_read_valid) , // input read_sig
177-
.write(adc_write_valid) , // input write_sig
178-
.readdataout(adc_data_out) , // output [31:0] readdataout_sig
179-
.writedatain(busdata_in) , // input [31:0] writedatain_sig
180-
//ADC
181-
.adc_clk(adc_clk) , // input adc_clk_sig
182-
.ADC_CONVST_o(ADC_CONVST_o) , // output ADC_CONVST_o_sig
183-
.ADC_SCK_o(ADC_SCK_o) , // output ADC_SCK_o_sig
184-
.ADC_SDI_o(ADC_SDI_o) , // output ADC_SDI_o_sig
185-
.ADC_SDO_i(ADC_SDO_i) // input ADC_SDO_i_sig
186-
);
173+
adc_ltc2308_fifo adc_ltc2308_fifo_inst
174+
(
175+
.clock(CLOCK) , // input clock_sig
176+
.reset_n(reset_reg_N) , // input reset_n_sig
177+
.addr(busaddress[2]) , // input addr_sig
178+
.read_outdata(adc_read_valid) , // input read_sig
179+
.write(adc_write_valid) , // input write_sig
180+
.readdataout(adc_data_out) , // output [31:0] readdataout_sig
181+
.writedatain(busdata_in) , // input [31:0] writedatain_sig
182+
//ADC
183+
.adc_clk(adc_clk) , // input adc_clk_sig
184+
.ADC_CONVST_o(ADC_CONVST_o) , // output ADC_CONVST_o_sig
185+
.ADC_SCK_o(ADC_SCK_o) , // output ADC_SCK_o_sig
186+
.ADC_SDI_o(ADC_SDI_o) , // output ADC_SDI_o_sig
187+
.ADC_SDO_i(ADC_SDO_i) // input ADC_SDO_i_sig
188+
);
187189

188190

189191
// I/O stuff:
@@ -259,26 +261,27 @@ adc_ltc2308_fifo adc_ltc2308_fifo_inst
259261
assign mux_reg_index = busaddress_r - 16'h1120;
260262
assign mux_reg_addr = (mux_reg_index[6:2]);
261263
assign mux_reg_byte = (mux_reg_index[1:0]);
262-
generate if (Capsense >= 1) begin
263-
// Writes:
264-
always @( posedge reset_in or posedge write_address) begin
265-
if (reset_in) begin
266-
hysteresis_reg <= 32'h22222222;
267-
reset_sr <= 1'b0;
268-
end
269-
else if ( write_address ) begin
270-
if (busaddress_r == 10'h0304) begin
271-
hysteresis_reg <= busdata_in_r;
272-
reset_sr <= 1'b1;
273-
end
274-
else begin
275-
hysteresis_reg <= hysteresis_reg;
264+
265+
generate if (Capsense >= 1) begin
266+
// Writes:
267+
always @( posedge reset_in or posedge write_address) begin
268+
if (reset_in) begin
269+
hysteresis_reg <= 32'h22222222;
276270
reset_sr <= 1'b0;
277271
end
278-
end
272+
else if ( write_address ) begin
273+
if (busaddress_r == 10'h0304) begin
274+
hysteresis_reg <= busdata_in_r;
275+
reset_sr <= 1'b1;
276+
end
277+
else begin
278+
hysteresis_reg <= hysteresis_reg;
279+
reset_sr <= 1'b0;
280+
end
281+
end
282+
end
279283
end
280-
end
281-
endgenerate
284+
endgenerate
282285

283286
always @(posedge reg_clk) begin
284287
sr_delay[0] <= reset_sr;
@@ -287,11 +290,11 @@ endgenerate
287290
sr_init_delay[1] <= sr_init_delay[0];
288291
sr_init_delay[2] <= sr_init_delay[1];
289292
end
290-
293+
291294
assign sr_delay_act = (sr_delay[1] == 1'b1 && sr_delay[0] == 1'b0) ? 1'b1 : 1'b0;
292295
assign sr_init_delay_act = (sr_init_delay[2] == 1'b0 && sr_init_delay[0] == 1'b1) ? 1'b1 : 1'b0;
293296
assign sense_reset = ~reset_reg_N | ~buttons[1] | sr_delay_act | sr_init_delay_act;
294-
297+
295298
genvar il;
296299
generate
297300
for(il=0;il<NumIOAddrReg;il=il+1) begin : reg_initloop
@@ -326,55 +329,68 @@ endgenerate
326329
end
327330
end
328331
endgenerate
329-
/*
330-
genvar bloop;
332+
333+
wire [((GPIOWidth * NumGPIO)-1):0] gpio_out_data;
334+
genvar cl,ci0,ci1;
331335
generate
332-
for(bloop=0;bloop<NumGPIO;bloop=bloop+1) begin : gpiooutloop
333-
bidir_io #(.IOWidth(GPIOWidth),.PortNumWidth(PortNumWidth)) bidir_io_inst
336+
if (Capsense >=1) begin
337+
for(cl=0;cl<(GPIOWidth * NumGPIO)-1;cl++) begin : capsenseloop
338+
// .out_data({iodatafromhm3[1][GPIOWidth-1:5],4'bz,charge, iodatafromhm3[0]}) , // input [IOIOWidth-1:0] out_data_sig
339+
if(cl<=35) begin
340+
if (Capsense_Pins[0] == cl) begin
341+
assign gpio_out_data[cl] = charge;
342+
end
343+
else begin
344+
for(ci0=1;ci0<NumSense+1;ci0++)begin : capsense0loop
345+
if(Capsense_Pins[ci0] == cl) begin
346+
assign gpio_out_data[cl] = 1'bz;
347+
end
348+
else begin
349+
assign gpio_out_data[cl] = iodatafromhm3[0][cl];
350+
end
351+
end
352+
end
353+
end
354+
else begin
355+
if (Capsense_Pins[0] == cl) begin
356+
assign gpio_out_data[cl] = charge;
357+
end
358+
else begin
359+
for(ci1=1;ci1<NumSense+1;ci1++) begin : capsense1loop
360+
if(Capsense_Pins[ci1] == cl) begin
361+
assign gpio_out_data[cl] = 1'bz;
362+
end
363+
else begin
364+
assign gpio_out_data[cl] = iodatafromhm3[1][cl-36];
365+
end
366+
end
367+
end
368+
end
369+
end
370+
bidir_io #(.IOWidth(GPIOWidth * NumGPIO),.PortNumWidth(PortNumWidth),.Mux_En(Mux_En)) bidir_io_inst
371+
(
372+
.clk(reg_clk),
373+
.portselnum(portnumsel),
374+
.out_ena({out_ena[1],out_ena[0]}) , // input out_ena_sig
375+
.od({od[1],od[0]}) , // input od_sig
376+
.out_data(gpio_out_data) , // input [IOIOWidth-1:0] out_data_sig
377+
.gpioport({gpioport[1],gpioport[0]}) , // inout [IOIOWidth-1:0] gpioport_sig
378+
.data_from_gpio({gpio_input_data[1],gpio_input_data[0]}) // output [IOIOWidth-1:0] read_data_sig
379+
);
380+
end
381+
else begin
382+
bidir_io #(.IOWidth(GPIOWidth * NumGPIO),.PortNumWidth(PortNumWidth),.Mux_En(Mux_En)) bidir_io_inst
334383
(
335384
.clk(reg_clk),
336-
.portselnum(portnumsel[bloop]),
337-
.out_ena(out_ena[bloop]) , // input out_ena_sig
338-
.od(od[bloop]) , // input od_sig
339-
.out_data(iodatafromhm3[bloop]) , // input [IOIOWidth-1:0] out_data_sig
340-
.gpioport(gpioport[bloop]) , // inout [IOIOWidth-1:0] gpioport_sig
341-
.gpio_in_data(gpio_input_data[bloop]) // output [IOIOWidth-1:0] read_data_sig
385+
.portselnum(portnumsel),
386+
.out_ena({out_ena[1],out_ena[0]}) , // input out_ena_sig
387+
.od({od[1],od[0]}) , // input od_sig
388+
.out_data({iodatafromhm3[1], iodatafromhm3[0]}) , // input [IOIOWidth-1:0] out_data_sig
389+
.gpioport({gpioport[1],gpioport[0]}) , // inout [IOIOWidth-1:0] gpioport_sig
390+
.data_from_gpio({gpio_input_data[1],gpio_input_data[0]}) // output [IOIOWidth-1:0] read_data_sig
342391
);
343-
// defparam bidir_io_inst[il].IOWidth = GPIOWidth;
344-
// defparam bidir_io_inst[il].PortNumWidth = PortNumWidth;
345392
end
346393
endgenerate
347-
*/
348-
349-
// wire [GPIOWidth-1:0] gpio1_data_fromhm3 = iodatafromhm3[1];
350-
// wire [GPIOWidth-1:0] gpio1_out_data = {gpio1_data_fromhm3[GPIOWidth-1:5],4'bz,charge};
351-
// wire [GPIOWidth-1:0] gpio1_input_data;
352-
// assign gpio_input_data[1] = {gpio1_input_data[GPIOWidth-1:5],sense,charge};
353-
generate if (Capsense >=1) begin
354-
bidir_io #(.IOWidth(GPIOWidth * NumGPIO),.PortNumWidth(PortNumWidth)) bidir_io_inst
355-
(
356-
.clk(reg_clk),
357-
.portselnum(portnumsel),
358-
.out_ena({out_ena[1],out_ena[0]}) , // input out_ena_sig
359-
.od({od[1],od[0]}) , // input od_sig
360-
.out_data({iodatafromhm3[1][GPIOWidth-1:5],4'bz,charge, iodatafromhm3[0]}) , // input [IOIOWidth-1:0] out_data_sig
361-
.gpioport({gpioport[1],gpioport[0]}) , // inout [IOIOWidth-1:0] gpioport_sig
362-
.data_from_gpio({gpio_input_data[1],gpio_input_data[0]}) // output [IOIOWidth-1:0] read_data_sig
363-
);
364-
end
365-
else begin
366-
bidir_io #(.IOWidth(GPIOWidth * NumGPIO),.PortNumWidth(PortNumWidth)) bidir_io_inst
367-
(
368-
.clk(reg_clk),
369-
.portselnum(portnumsel),
370-
.out_ena({out_ena[1],out_ena[0]}) , // input out_ena_sig
371-
.od({od[1],od[0]}) , // input od_sig
372-
.out_data({iodatafromhm3[1], iodatafromhm3[0]}) , // input [IOIOWidth-1:0] out_data_sig
373-
.gpioport({gpioport[1],gpioport[0]}) , // inout [IOIOWidth-1:0] gpioport_sig
374-
.data_from_gpio({gpio_input_data[1],gpio_input_data[0]}) // output [IOIOWidth-1:0] read_data_sig
375-
);
376-
end
377-
endgenerate
378394
// Read:
379395

380396
integer oo,om,oi;
@@ -413,8 +429,8 @@ endgenerate
413429
else begin busdata_to_cpu <= busdata_fromhm2; end
414430
end else begin
415431
if (adc_address_valid) begin busdata_to_cpu <= adc_data_out; end
416-
// if ((busaddress_r == 'h0200) || (busaddress_r == 'h0204)) begin busdata_to_cpu <= adc_data_out; end
417-
else if (busaddress_r == 'h0304) begin busdata_to_cpu <= hysteresis_reg; end
432+
// else if (busaddress_r == 'h0300) begin busdata_to_cpu <= touched; reset_init_sr <= 1'b1; end
433+
// else if (busaddress_r == 'h0304) begin busdata_to_cpu <= hysteresis_reg; end
418434
else if(busaddress_r == 'h1000) begin busdata_to_cpu <= {8'b0,gpio_input_data[0][23:0]}; end
419435
else if(busaddress_r == 'h1004) begin busdata_to_cpu <= {8'b0,gpio_input_data[1][11:0],gpio_input_data[0][35:24]}; end
420436
else if(busaddress_r == 'h1008) begin busdata_to_cpu <= {8'b0,gpio_input_data[1][35:12]}; end
@@ -441,30 +457,30 @@ endgenerate
441457
end
442458
endgenerate
443459

444-
generate if (Capsense >=1) begin
445-
assign sense = gpio_input_data[1][5:1];
446-
447-
capsense capsense_inst
448-
(
449-
.clk(reg_clk) , // input clk_sig
450-
.reset(sense_reset) , // input reset_sig
451-
.sense(sense) , // input [num-1:0] sense_sig
452-
.hysteresis(hysteresis),
453-
// .calibval_0(calibval_0),
454-
// .counts_0(counts_0),
455-
.charge(charge) , // output charge_sig
456-
.touched(touched) // output [num-1:0] touched_sig
457-
);
458-
459-
defparam capsense_inst.num = NumSense;
460-
// States
461-
defparam capsense_inst.CHARGE = 1;
462-
defparam capsense_inst.DISCHARGE = 2;
463-
// freqwuency in Mhz , times in us
464-
defparam capsense_inst.clockfrequency = 200;
465-
defparam capsense_inst.periodtime = 5;
466-
end
467-
endgenerate
460+
generate if (Capsense >=1) begin
461+
assign sense = gpio_input_data[1][5:1];
462+
463+
capsense capsense_inst
464+
(
465+
.clk(reg_clk) , // input clk_sig
466+
.reset(sense_reset) , // input reset_sig
467+
.sense(sense) , // input [num-1:0] sense_sig
468+
.hysteresis(hysteresis),
469+
// .calibval_0(calibval_0),
470+
// .counts_0(counts_0),
471+
.charge(charge) , // output charge_sig
472+
.touched(touched) // input [num-1:0] touched_sig
473+
);
474+
475+
defparam capsense_inst.num = NumSense;
476+
// States
477+
defparam capsense_inst.CHARGE = 1;
478+
defparam capsense_inst.DISCHARGE = 2;
479+
// freqwuency in Mhz , times in us
480+
defparam capsense_inst.clockfrequency = 200;
481+
defparam capsense_inst.periodtime = 5;
482+
end
483+
endgenerate
468484

469485
endmodule
470486

‎HW/QuartusProjects/DE0_Nano_SoC_Cramps/DE0_Nano_SoC_Cramps.sv‎

Lines changed: 4 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -160,8 +160,6 @@ parameter NumIOAddrReg = 6;
160160
wire hm_clk_high;
161161
wire adc_clk_40;
162162
// wire clklow_sig;
163-
wire clkmed_sig;
164-
wire clkhigh_sig;
165163

166164
// Mesa I/O Signals:
167165
wire [LEDCount-1:0] hm2_leds_sig;
@@ -315,10 +313,6 @@ defparam top_io_modules_inst.KEY_WIDTH = 2;
315313

316314
// Mesa code ------------------------------------------------------//
317315

318-
assign clkhigh_sig = hm_clk_high;
319-
assign clkmed_sig = hm_clk_med;
320-
321-
322316
genvar ig;
323317
generate for(ig=0;ig<NumGPIO;ig=ig+1) begin : iosigloop
324318
assign io_bitsout_sig[ig] = hm2_bitsout_sig[(ig*MuxGPIOIOWidth)+:MuxGPIOIOWidth];
@@ -329,7 +323,7 @@ endgenerate
329323
gpio_adr_decoder_reg gpio_adr_decoder_reg_inst
330324
(
331325
.CLOCK(fpga_clk_50) , // input CLOCK_sig
332-
.reg_clk(clkhigh_sig) , // input CLOCK_sig
326+
.reg_clk(hm_clk_high) , // input CLOCK_sig
333327
.reset_reg_N(hps_fpga_reset_n) , // input reset_reg_N_sig
334328
.chip_sel(hm_chipsel[0]) , // input data_ready_sig
335329
.write_reg(hm_write) , // input data_ready_sig
@@ -362,6 +356,7 @@ defparam gpio_adr_decoder_reg_inst.NumGPIO = NumGPIO;
362356
defparam gpio_adr_decoder_reg_inst.ADC = ADC;
363357
defparam gpio_adr_decoder_reg_inst.Capsense = Capsense;
364358
defparam gpio_adr_decoder_reg_inst.NumSense = NumSense;
359+
defparam gpio_adr_decoder_reg_inst.Capsense_Pins = Capsense_Pins;
365360

366361
HostMot3_cfg HostMot3_inst
367362
(
@@ -372,8 +367,8 @@ HostMot3_cfg HostMot3_inst
372367
.writestb(hm_write) , // input writestb_sig
373368

374369
.clklow(fpga_clk_50) , // input clklow_sig -- PCI clock --> all
375-
.clkmed(clkmed_sig) , // input clkmed_sig -- Processor clock --> sserialwa, twiddle
376-
.clkhigh(clkhigh_sig) , // input clkhigh_sig -- High speed clock --> most
370+
.clkmed(hm_clk_med) , // input hm_clk_med -- Processor clock --> sserialwa, twiddle
371+
.clkhigh(hm_clk_high) , // input hm_clk_high -- High speed clock --> most
377372
.intirq(int_sig) , // output int_sig --int => LINT, ---> PCI ?
378373
.iobitsouttop(hm2_bitsout_sig) , // inout [IOWidth-1:0] --iobits => IOBITS,-- external I/O bits
379374
.iobitsintop(hm2_bitsin_sig) // inout [IOWidth-1:0] --iobits => IOBITS,-- external I/O bits

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