Skip to content

Commit 1666f27

Browse files
the-snowwhitethe-snowwhite
committed
add Myirtech FZ3 arm64-socfpga board
Signed-off-by: Holotronic <producer@holotronic.dk>
1 parent c39d5ad commit 1666f27

File tree

7 files changed

+2127
-0
lines changed

7 files changed

+2127
-0
lines changed

‎HW/VivadoProjects/make_mpsoc_boot.sh‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,9 @@ CUR_DIR=`realpath .`
2020
if [[ $1 == *"ultra96"* ]]; then
2121
cd /work/avnet/ultra96
2222
BOARD_PART="xczu3eg"
23+
else if [[ $1 == *"fz3"* ]]; then
24+
cd /work//myirtech/fz3
25+
BOARD_PART="xczu3eg"
2326
else
2427
echo "cant't find board project folder"
2528
exit 1

‎HW/VivadoProjects/myirtech/fz3/const/PIN_FZ3_36.vhd‎

Lines changed: 170 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,170 @@
1+
library IEEE;
2+
use IEEE.std_logic_1164.all; -- defines std_logic types
3+
use IEEE.STD_LOGIC_ARITH.ALL;
4+
use IEEE.STD_LOGIC_UNSIGNED.ALL;
5+
6+
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
7+
-- http://www.mesanet.com
8+
--
9+
-- Ported to MYIR ZTURN IO Carrier board:
10+
-- Copyright (C) 2016, Devin Hughes, JD Squared
11+
-- http://www.jd2.com
12+
--
13+
-- This program is is licensed under a disjunctive dual license giving you
14+
-- the choice of one of the two following sets of free software/open source
15+
-- licensing terms:
16+
--
17+
-- * GNU General Public License (GPL), version 2.0 or later
18+
-- * 3-clause BSD License
19+
--
20+
--
21+
-- The GNU GPL License:
22+
--
23+
-- This program is free software; you can redistribute it and/or modify
24+
-- it under the terms of the GNU General Public License as published by
25+
-- the Free Software Foundation; either version 2 of the License, or
26+
-- (at your option) any later version.
27+
--
28+
-- This program is distributed in the hope that it will be useful,
29+
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
30+
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31+
-- GNU General Public License for more details.
32+
--
33+
-- You should have received a copy of the GNU General Public License
34+
-- along with this program; if not, write to the Free Software
35+
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
36+
--
37+
--
38+
-- The 3-clause BSD License:
39+
--
40+
-- Redistribution and use in source and binary forms, with or without
41+
-- modification, are permitted provided that the following conditions
42+
-- are met:
43+
--
44+
-- * Redistributions of source code must retain the above copyright
45+
-- notice, this list of conditions and the following disclaimer.
46+
--
47+
-- * Redistributions in binary form must reproduce the above
48+
-- copyright notice, this list of conditions and the following
49+
-- disclaimer in the documentation and/or other materials
50+
-- provided with the distribution.
51+
--
52+
-- * Neither the name of Mesa Electronics nor the names of its
53+
-- contributors may be used to endorse or promote products
54+
-- derived from this software without specific prior written
55+
-- permission.
56+
--
57+
--
58+
-- Disclaimer:
59+
--
60+
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
61+
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
62+
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
63+
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
64+
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
65+
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
66+
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
67+
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
68+
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
69+
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
70+
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
71+
-- POSSIBILITY OF SUCH DAMAGE.
72+
--
73+
74+
use work.IDROMConst.all;
75+
76+
package PIN_FZ3_36 is
77+
constant ModuleID : ModuleIDType :=(
78+
(HM2DPLLTag, x"00", ClockLowTag, x"04", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
79+
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
80+
(QcountTag, x"02", ClockLowTag, x"02", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
81+
(StepGenTag, x"02", ClockLowTag, x"08", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
82+
(FWIDTag, x"00", ClockLowTag, x"01", FWIDAddr&PadT, FWIDNumRegs, x"00", FWIDMPBitMask),
83+
(PWMTag, x"00", ClockHighTag, x"03", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
84+
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
85+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
86+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
87+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
88+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
89+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
90+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
91+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
92+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
93+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
94+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
95+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
96+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
97+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
98+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
99+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
100+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
101+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
102+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
103+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
104+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
105+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
106+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
107+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
108+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
109+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
110+
);
111+
112+
113+
constant PinDesc : PinDescType :=(
114+
-- Base func sec unit sec func sec pin -- hostmot2 Header Pin Func HD = 3V3, SD = 1V8
115+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 00 HD_GPIO0_0 J15_11 GPIO
116+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 01 HD_GPIO0_1 J15_12 GPIO
117+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 02 HD_GPIO0_2 J15_13 GPIO
118+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 03 HD_GPIO0_3 J15_14 GPIO
119+
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 04 HD_GPIO0_4 J15_15 A Dir
120+
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 05 HD_GPIO0_5 J15_16 A Step
121+
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 06 HD_GPIO0_6 J15_17 B Dir
122+
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 07 HD_GPIO0_7 J15_18 B Step
123+
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 08 HD_GPIO0_8 J16_21 C Dir
124+
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 09 HD_GPIO0_9 J16_22 C Step
125+
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 10 HD_GPIO0_10 J16_23 D Dir
126+
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 11 HD_GPIO0_11 J16_24 D Step
127+
IOPortTag & x"00" & HM2DPLLTag & HM2DPLLRefOutPin, -- I/O 12 HD_GPIO0_12 J16_25 DPLL Ref Output
128+
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 13 HD_GPIO0_14 J16_26 Input 1 (Quad A)
129+
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 14 HD_GPIO0_14 J16_27 Input 2 (Quad B)
130+
IOPortTag & x"00" & QCountTag & QCountIdxPin, -- I/O 15 HD_GPIO0_15 J16_28 Input 3 (Quad Idx)
131+
132+
-- Base func sec unit sec func sec pin -- hostmot2 Header Pin Func
133+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 16 HD_GPIO0_16 J16_31 GPIO
134+
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 17 HD_GPIO0_17 J16_32 PWM
135+
IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 18 HD_GPIO0_18 J16_33 PWM
136+
IOPortTag & x"02" & PWMTag & PWMAOutPin, -- I/O 19 HD_GPIO0_19 J16_34 PWM
137+
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 20 HD_GPIO0_20 J16_35 E Dir
138+
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 21 HD_GPIO0_21 J16_36 E Step
139+
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 22 HD_GPIO0_22 J16_37 F Dir
140+
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 23 HD_GPIO0_23 J16_38 F Step
141+
IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 24 SD_GPIO0_24 J15_21 G Dir
142+
IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 25 SD_GPIO0_25 J15_22 G Step
143+
IOPortTag & x"07" & StepGenTag & StepGenDirPin, -- I/O 26 SD_GPIO0_26 J15_23 H Dir
144+
IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 27 SD_GPIO0_27 J15_24 H Step
145+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 28 SD_GPIO0_28 J15_25 GPIO
146+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 29 SD_GPIO0_29 J15_26 GPIO
147+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 30 SD_GPIO0_30 J15_27 GPIO
148+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 31 SD_GPIO0_31 J15_28 GPIO
149+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 32 SD_GPIO0_32 J15_31 GPIO
150+
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 33 SD_GPIO0_33 J15_32 Input 1 (Quad A)
151+
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 34 SD_GPIO0_34 J15_33 Input 2 (Quad B)
152+
IOPortTag & x"01" & QCountTag & QCountIdxPin, -- I/O 35 SD_GPIO0_35 J15_34 Input 3 (Quad Idx)
153+
154+
-- Fill remaining 144 pins
155+
emptypin,emptypin,emptypin,emptypin,
156+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
157+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
158+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
159+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
160+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
161+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
162+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
163+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
164+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
165+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
166+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
167+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
168+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
169+
170+
end package PIN_FZ3_36;

‎HW/VivadoProjects/myirtech/fz3/const/fz3_pinmap.xdc‎

Lines changed: 59 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,59 @@
1+
#fan pwm control
2+
#set_property PACKAGE_PIN AD14 [get_ports {FAN_PWM}]
3+
#set_property IOSTANDARD LVCMOS33 [get_ports FAN_PWM]
4+
5+
#######################################################################
6+
# Ultra96 MESA Hostmot2 Signals
7+
#######################################################################
8+
set_property PACKAGE_PIN B11 [get_ports {IOBits[0]}]; # "B11.HD_L10P_25"
9+
set_property PACKAGE_PIN E12 [get_ports {IOBits[1]}]; # "E12.HD_L08P_25"
10+
set_property PACKAGE_PIN A10 [get_ports {IOBits[2]}]; # "A10.HD_L10N_25"
11+
set_property PACKAGE_PIN D11 [get_ports {IOBits[3]}]; # "D11.HD_L08N_25"
12+
set_property PACKAGE_PIN F12 [get_ports {IOBits[4]}]; # "F12.HD_L06P_25"
13+
set_property PACKAGE_PIN G13 [get_ports {IOBits[5]}]; # "G13.HD_L07P_26"
14+
set_property PACKAGE_PIN F11 [get_ports {IOBits[6]}]; # "F11.HD_L06N_25"
15+
set_property PACKAGE_PIN F13 [get_ports {IOBits[7]}]; # "F13.HD_L07N_26"
16+
set_property PACKAGE_PIN E10 [get_ports {IOBits[8]}]; # "E10.HD_L07P_25"
17+
set_property PACKAGE_PIN G11 [get_ports {IOBits[9]}]; # "G11.HD_L05P_25"
18+
set_property PACKAGE_PIN D10 [get_ports {IOBits[10]}]; # "D10.HD_L07N_25"
19+
set_property PACKAGE_PIN F10 [get_ports {IOBits[11]}]; # "F10.HD_L05N_25"
20+
set_property PACKAGE_PIN A12 [get_ports {IOBits[12]}]; # "A12.HD_L11P_25"
21+
set_property PACKAGE_PIN C11 [get_ports {IOBits[13]}]; # "C11.HD_L09P_25"
22+
set_property PACKAGE_PIN A11 [get_ports {IOBits[14]}]; # "A11.HD_L11N_25"
23+
set_property PACKAGE_PIN B10 [get_ports {IOBits[15]}]; # "B10.HD_L09N_25"
24+
set_property PACKAGE_PIN E14 [get_ports {IOBits[16]}]; # "E14.HD_L06P_26"
25+
set_property PACKAGE_PIN B13 [get_ports {IOBits[17]}]; # "B13.HD_L03P_26"
26+
set_property PACKAGE_PIN E13 [get_ports {IOBits[18]}]; # "E13.HD_L06N_26"
27+
set_property PACKAGE_PIN A13 [get_ports {IOBits[19]}]; # "A13.HD_L03N_26"
28+
set_property PACKAGE_PIN F15 [get_ports {IOBits[20]}]; # "F15.HD_L08P_26"
29+
set_property PACKAGE_PIN H14 [get_ports {IOBits[21]}]; # "H14.HD_L10P_26"
30+
set_property PACKAGE_PIN E15 [get_ports {IOBits[22]}]; # "E15.HD_L08N_26"
31+
set_property PACKAGE_PIN H13 [get_ports {IOBits[23]}]; # "M4.HD_L10N_26"
32+
set_property PACKAGE_PIN A2 [get_ports {IOBits[24]}]; # "A2.HP_BANK66_L08_P"
33+
set_property PACKAGE_PIN C1 [get_ports {IOBits[25]}]; # "C1.HP_BANK66_L07_P"
34+
set_property PACKAGE_PIN A1 [get_ports {IOBits[26]}]; # "A1.HP_BANK66_L08_N"
35+
set_property PACKAGE_PIN B1 [get_ports {IOBits[27]}]; # "B1.HP_BANK66_L07_N"
36+
set_property PACKAGE_PIN C3 [get_ports {IOBits[28]}]; # "C3.HP_BANK66_L12_P"
37+
set_property PACKAGE_PIN E1 [get_ports {IOBits[29]}]; # "E1.HP_BANK66_L02_P"
38+
set_property PACKAGE_PIN C2 [get_ports {IOBits[30]}]; # "C2.HP_BANK66_L12_N"
39+
set_property PACKAGE_PIN D1 [get_ports {IOBits[31]}]; # "D1.HP_BANK66_L02_N"
40+
set_property PACKAGE_PIN G1 [get_ports {LED[0]}]; # "G1.HP_BANK66_L01_P"
41+
set_property PACKAGE_PIN J1 [get_ports {IOBits[32]}]; # "J1.HP_BANK65_L08_P"
42+
set_property PACKAGE_PIN F1 [get_ports {IOBits[33]}]; # "F1.HP_BANK66_L01_N"
43+
set_property PACKAGE_PIN H1 [get_ports {IOBits[34]}]; # "H1.HP_BANK65_L08_N"
44+
set_property PACKAGE_PIN L1 [get_ports {IOBits[35]}]; # "L1.HP_BANK65_L07_P"
45+
set_property PACKAGE_PIN L3 [get_ports {RATES[0]}]; # "L3.HP_BANK65_L12_P"
46+
set_property PACKAGE_PIN K1 [get_ports {RATES[1]}]; # "K1.HP_BANK65_L07_N"
47+
set_property PACKAGE_PIN L2 [get_ports {RATES[2]}]; # "L2.HP_BANK65_L12_N"
48+
49+
# Set the bank voltage for IO Bank 25 to 3.3V
50+
set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 25]]
51+
52+
# Set the bank voltage for IO Bank 26 to 3.3V
53+
set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 26]]
54+
55+
# Set the bank voltage for IO Bank 65 to 1.8V
56+
set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 65]]
57+
58+
# Set the bank voltage for IO Bank 66 to 1.8V
59+
set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 66]]

‎HW/VivadoProjects/myirtech/fz3/fz3-mk-2019.1.bsp‎

4.49 MB
Binary file not shown.

‎HW/VivadoProjects/myirtech/fz3/fz3_config‎

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,40 @@
1+
#!/bin/sh
2+
3+
# TCL Template Filename
4+
TCL_TEMP_FILE=../../zynqmp_bp.tcl.in
5+
6+
# The fpga device we are building for
7+
FPGA_DEVICE=xczu3eg-sfvc784-1-e
8+
FPGA_DEV_SHORT=xczu3eg
9+
10+
# Base Project Name
11+
BOARD_NAME=fz3
12+
PRJ_NAME="$BOARD_NAME"_"$FPGA_DEV_SHORT"
13+
14+
# The board part file url, if the target has one
15+
BOARD_PART="myirtech.com:fz3:part0:1.0"
16+
17+
# The physical package pin constraint file
18+
PIN_HW_XDC_FILE=const/fz3_pinmap.xdc
19+
20+
# The filename of the top level block diagram
21+
TOP_LEVEL_BD_FILE=scripts/soc_system.tcl
22+
23+
## HostMot2 Pin constraints - these update the IP. Physical pin constraints
24+
# belong in an xdc file above
25+
26+
# HM2 Pin Filename relative to project folder
27+
PIN_FILE=const/PIN_FZ3_36.vhd
28+
# Pin package name defined in above pin file
29+
PIN_NAME=PIN_FZ3_36
30+
#FWID File name in the const folder
31+
FWID_NAME=FWID_FZ3_36
32+
33+
############################################################################
34+
# HostMot2 Generic Parameters, autofills IP correctly without regenerating
35+
# block diagram script
36+
############################################################################
37+
38+
# The name of the board to compile into the IP. Matches board name in hal files
39+
BOARD_NAME_HIGH_HEX=5F335A46 #FZ3_
40+
BOARD_NAME_LOW_HEX=5249594D #MYIR

0 commit comments

Comments
 (0)