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[Sparc] Optimize compare instruction #167140

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[Sparc] Optimize compare instruction #167140

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143 changes: 143 additions & 0 deletions llvm/lib/Target/Sparc/SparcInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -640,6 +640,149 @@ unsigned SparcInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
return get(Opcode).getSize();
}

bool SparcInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
Register &SrcReg2, int64_t &CmpMask,
int64_t &CmpValue) const {
switch (MI.getOpcode()) {
default:
break;
case SP::CMPri:
SrcReg = MI.getOperand(0).getReg();
SrcReg2 = 0;
CmpMask = ~0;
CmpValue = MI.getOperand(1).getImm();
return (CmpValue == 0);
case SP::CMPrr:
SrcReg = MI.getOperand(0).getReg();
SrcReg2 = MI.getOperand(1).getReg();
CmpMask = ~0;
CmpValue = 0;
return SrcReg2 == SP::G0;
}

return false;
}

bool SparcInstrInfo::optimizeCompareInstr(
MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask,
int64_t CmpValue, const MachineRegisterInfo *MRI) const {

// Get the unique definition of SrcReg.
MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
if (!MI)
return false;

// Only optimize if defining and comparing instruction in same block.
if (MI->getParent() != CmpInstr.getParent())
return false;

unsigned newOpcode;
switch (MI->getOpcode()) {
case SP::ANDNrr:
newOpcode = SP::ANDNCCrr;
break;
case SP::ANDNri:
newOpcode = SP::ANDNCCri;
break;
case SP::ANDrr:
newOpcode = SP::ANDCCrr;
break;
case SP::ANDri:
newOpcode = SP::ANDCCri;
break;
case SP::ORrr:
newOpcode = SP::ORCCrr;
break;
case SP::ORri:
newOpcode = SP::ORCCri;
break;
case SP::ORNCCrr:
newOpcode = SP::ORNCCrr;
break;
case SP::ORNri:
newOpcode = SP::ORNCCri;
break;
case SP::XORrr:
newOpcode = SP::XORCCrr;
break;
case SP::XNORri:
newOpcode = SP::XNORCCri;
break;
case SP::XNORrr:
newOpcode = SP::XNORCCrr;
break;
case SP::ADDrr:
newOpcode = SP::ADDCCrr;
break;
case SP::ADDri:
newOpcode = SP::ADDCCri;
break;
case SP::SUBrr:
newOpcode = SP::SUBCCrr;
break;
case SP::SUBri:
newOpcode = SP::SUBCCri;
break;
default:
return false;
}

bool isSafe = false;
bool isRegUsed = false;
MachineBasicBlock::iterator I = MI;
MachineBasicBlock::iterator C = CmpInstr;
MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
const TargetRegisterInfo *TRI = &getRegisterInfo();

// If ICC is used or modified between MI and CmpInstr we cannot optimize.
while (++I != C) {
if (I->modifiesRegister(SP::ICC, TRI) || I->readsRegister(SP::ICC, TRI))
return false;
if (I->readsRegister(SrcReg, TRI))
isRegUsed = true;
}

while (++I != E) {
// Only allow conditionals on equality.
if (I->readsRegister(SP::ICC, TRI)) {
bool IsICCBranch = (I->getOpcode() == SP::BCOND) ||
(I->getOpcode() == SP::BPICC) ||
(I->getOpcode() == SP::BPXCC);
bool IsICCMove = (I->getOpcode() == SP::MOVICCrr) ||
(I->getOpcode() == SP::MOVICCri) ||
(I->getOpcode() == SP::MOVXCCrr) ||
(I->getOpcode() == SP::MOVXCCri);
bool IsICCConditional = IsICCBranch || IsICCMove;
if (!IsICCConditional ||
(I->getOperand(IsICCBranch ? 1 : 3).getImm() != SPCC::ICC_E &&
I->getOperand(IsICCBranch ? 1 : 3).getImm() != SPCC::ICC_NE))
return false;
} else if (I->modifiesRegister(SP::ICC, TRI)) {
isSafe = true;
break;
}
}

if (!isSafe) {
MachineBasicBlock *MBB = CmpInstr.getParent();
for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
SE = MBB->succ_end();
SI != SE; ++SI)
if ((*SI)->isLiveIn(SP::ICC))
return false;
}

// If the result is not needed use the %g0 register.
if (!isRegUsed && CmpInstr.getOperand(0).isKill())
MI->getOperand(0).setReg(SP::G0);

MI->setDesc(get(newOpcode));
MI->addRegisterDefined(SP::ICC);
CmpInstr.eraseFromParent();

return true;
}

bool SparcInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
switch (MI.getOpcode()) {
case TargetOpcode::LOAD_STACK_GUARD: {
Expand Down
8 changes: 8 additions & 0 deletions llvm/lib/Target/Sparc/SparcInstrInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -108,6 +108,14 @@ class SparcInstrInfo : public SparcGenInstrInfo {
/// instruction may be. This returns the maximum number of bytes.
unsigned getInstSizeInBytes(const MachineInstr &MI) const override;

bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
Register &SrcReg2, int64_t &CmpMask,
int64_t &CmpValue) const override;

bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
const MachineRegisterInfo *MRI) const override;

// Lower pseudo instructions after register allocation.
bool expandPostRAPseudo(MachineInstr &MI) const override;
};
Expand Down
13 changes: 11 additions & 2 deletions llvm/lib/Target/Sparc/SparcInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -914,8 +914,17 @@ let Defs = [ICC], hasPostISelHook = true in
let Uses = [ICC] in
defm SUBC : F3_12np <"subx", 0b001100>;

def : Pat<(SPcmpicc i32:$lhs, i32:$rhs), (SUBCCrr $lhs, $rhs)>;
def : Pat<(SPcmpicc i32:$lhs, (i32 simm13:$rhs)), (SUBCCri $lhs, imm:$rhs)>;
// cmp (from Section A.3) is a specialized alias for subcc
let Defs = [ICC], rd = 0, isCompare = 1 in {
def CMPrr : F3_1<2, 0b010100,
(outs), (ins IntRegs:$rs1, IntRegs:$rs2),
"cmp $rs1, $rs2",
[(SPcmpicc i32:$rs1, i32:$rs2)]>;
def CMPri : F3_2<2, 0b010100,
(outs), (ins IntRegs:$rs1, simm13Op:$simm13),
"cmp $rs1, $simm13",
[(SPcmpicc i32:$rs1, (i32 simm13:$simm13))]>;
}
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@s-barannikov s-barannikov Nov 8, 2025

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These instructions don't exist, that's why I removed them.
If the only reason you added them back is isCompare flag, it should be set on the corresponding real instructions.


// Section B.18 - Multiply Instructions, p. 113
let Defs = [Y] in {
Expand Down
6 changes: 2 additions & 4 deletions llvm/test/CodeGen/SPARC/2011-01-11-CC.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -25,15 +25,13 @@ define i32 @test_addx(i64 %a, i64 %b, i64 %c) nounwind {
; V8-NEXT: retl
; V8-NEXT: nop
; V8-NEXT: .LBB0_4: ! %entry
; V8-NEXT: mov %g0, %o2
; V8-NEXT: cmp %o3, %o5
; V8-NEXT: bgu .LBB0_2
; V8-NEXT: nop
; V8-NEXT: mov %g0, %o2
; V8-NEXT: .LBB0_5: ! %entry
; V8-NEXT: mov %g0, %o0
; V8-NEXT: cmp %o1, %o4
; V8-NEXT: be .LBB0_3
; V8-NEXT: nop
; V8-NEXT: mov %g0, %o0
; V8-NEXT: .LBB0_6: ! %entry
; V8-NEXT: retl
; V8-NEXT: mov %o2, %o0
Expand Down
6 changes: 2 additions & 4 deletions llvm/test/CodeGen/SPARC/atomicrmw-uinc-udec-wrap.ll
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Expand Up @@ -292,17 +292,15 @@ define i64 @atomicrmw_udec_wrap_i64(ptr %ptr, i64 %val) {
; CHECK-NEXT: mov %g0, %l0
; CHECK-NEXT: addcc %g3, -1, %o3
; CHECK-NEXT: addxcc %g2, -1, %o2
; CHECK-NEXT: or %g3, %g2, %l1
; CHECK-NEXT: cmp %l1, 0
; CHECK-NEXT: orcc %g3, %g2, %g0
; CHECK-NEXT: move %icc, 1, %i5
; CHECK-NEXT: cmp %g2, %i1
; CHECK-NEXT: movgu %icc, 1, %g4
; CHECK-NEXT: cmp %g3, %i2
; CHECK-NEXT: movgu %icc, 1, %l0
; CHECK-NEXT: cmp %g2, %i1
; CHECK-NEXT: move %icc, %l0, %g4
; CHECK-NEXT: or %i5, %g4, %i5
; CHECK-NEXT: cmp %i5, 0
; CHECK-NEXT: orcc %i5, %g4, %i5
; CHECK-NEXT: movne %icc, %i1, %o2
; CHECK-NEXT: movne %icc, %i2, %o3
; CHECK-NEXT: std %g2, [%fp+-8]
Expand Down
6 changes: 2 additions & 4 deletions llvm/test/CodeGen/SPARC/ctlz.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -156,8 +156,7 @@ define i64 @i64_nopoison(i64 %x) nounwind {
; SPARC-LABEL: i64_nopoison:
; SPARC: ! %bb.0:
; SPARC-NEXT: save %sp, -96, %sp
; SPARC-NEXT: or %i1, %i0, %i2
; SPARC-NEXT: cmp %i2, 0
; SPARC-NEXT: orcc %i1, %i0, %g0
; SPARC-NEXT: be .LBB2_4
; SPARC-NEXT: nop
; SPARC-NEXT: ! %bb.1: ! %cond.false
Expand All @@ -182,8 +181,7 @@ define i64 @i64_nopoison(i64 %x) nounwind {
; SPARC-POPC-LABEL: i64_nopoison:
; SPARC-POPC: ! %bb.0:
; SPARC-POPC-NEXT: save %sp, -96, %sp
; SPARC-POPC-NEXT: or %i1, %i0, %i2
; SPARC-POPC-NEXT: cmp %i2, 0
; SPARC-POPC-NEXT: orcc %i1, %i0, %g0
; SPARC-POPC-NEXT: be .LBB2_4
; SPARC-POPC-NEXT: nop
; SPARC-POPC-NEXT: ! %bb.1: ! %cond.false
Expand Down
6 changes: 2 additions & 4 deletions llvm/test/CodeGen/SPARC/cttz.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -184,8 +184,7 @@ define i32 @i32_poison(i32 %x) nounwind {
define i64 @i64_nopoison(i64 %x) nounwind {
; SPARC-LABEL: i64_nopoison:
; SPARC: ! %bb.0:
; SPARC-NEXT: or %o1, %o0, %o2
; SPARC-NEXT: cmp %o2, 0
; SPARC-NEXT: orcc %o1, %o0, %g0
; SPARC-NEXT: be .LBB2_3
; SPARC-NEXT: nop
; SPARC-NEXT: ! %bb.1: ! %cond.false
Expand Down Expand Up @@ -219,8 +218,7 @@ define i64 @i64_nopoison(i64 %x) nounwind {
;
; SPARC-POPC-LABEL: i64_nopoison:
; SPARC-POPC: ! %bb.0:
; SPARC-POPC-NEXT: or %o1, %o0, %o2
; SPARC-POPC-NEXT: cmp %o2, 0
; SPARC-POPC-NEXT: orcc %o1, %o0, %g0
; SPARC-POPC-NEXT: be .LBB2_3
; SPARC-POPC-NEXT: nop
; SPARC-POPC-NEXT: ! %bb.1: ! %cond.false
Expand Down
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