[AMDGPU] clang-tidy: use emplace_back instead of push_back. NFC.

Author: jayfoad

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

@@ -285,7 +285,7 @@ void AMDGPUAsmPrinter::emitFunctionEntryLabel() {
     // Disassemble function name label to text.
     DisasmLines.push_back(MF->getName().str() + ":");
     DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLines.back().size());
-    HexLines.push_back("");
+    HexLines.emplace_back("");
   }
 
   AsmPrinter::emitFunctionEntryLabel();
@@ -298,7 +298,7 @@ void AMDGPUAsmPrinter::emitBasicBlockStart(const MachineBasicBlock &MBB) {
         (Twine("BB") + Twine(getFunctionNumber())
          + "_" + Twine(MBB.getNumber()) + ":").str());
     DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLines.back().size());
-    HexLines.push_back("");
+    HexLines.emplace_back("");
   }
   AsmPrinter::emitBasicBlockStart(MBB);
 }

llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp

@@ -2466,7 +2466,7 @@ int SchedGroup::link(SUnit &SU, bool MakePred,
     // the A->B edge impossible, otherwise it returns true;
     bool Added = tryAddEdge(A, B);
     if (Added)
-      AddedEdges.push_back(std::pair(A, B));
+      AddedEdges.emplace_back(A, B);
     else
       ++MissedEdges;
   }

llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp

@@ -480,7 +480,7 @@ doPartitioning(SplitModuleLogger &SML, Module &M, unsigned NumParts,
   // partitions) so it's a cheap operation.
   std::vector<std::pair<PartitionID, CostType>> BalancingQueue;
   for (unsigned I = 0; I < NumParts; ++I)
-    BalancingQueue.push_back(std::make_pair(I, 0));
+    BalancingQueue.emplace_back(I, 0);
 
   // Helper function to handle assigning a function to a partition. This takes
   // care of updating the balancing queue.

llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp

@@ -169,7 +169,7 @@ BasicBlock *AMDGPUUnifyDivergentExitNodesImpl::unifyReturnBlockSet(
     // Remove and delete the return inst.
     BB->getTerminator()->eraseFromParent();
     BranchInst::Create(NewRetBlock, BB);
-    Updates.push_back({DominatorTree::Insert, BB, NewRetBlock});
+    Updates.emplace_back(DominatorTree::Insert, BB, NewRetBlock);
   }
 
   if (RequireAndPreserveDomTree)
@@ -239,7 +239,7 @@ bool AMDGPUUnifyDivergentExitNodesImpl::run(Function &F, DominatorTree *DT,
         BI->eraseFromParent(); // Delete the unconditional branch.
         // Add a new conditional branch with a dummy edge to the return block.
         BranchInst::Create(LoopHeaderBB, DummyReturnBB, BoolTrue, BB);
-        Updates.push_back({DominatorTree::Insert, BB, DummyReturnBB});
+        Updates.emplace_back(DominatorTree::Insert, BB, DummyReturnBB);
       } else { // Conditional branch.
         SmallVector<BasicBlock *, 2> Successors(successors(BB));
 
@@ -250,17 +250,17 @@ bool AMDGPUUnifyDivergentExitNodesImpl::run(Function &F, DominatorTree *DT,
 
         // 'Successors' become successors of TransitionBB instead of BB,
         // and TransitionBB becomes a single successor of BB.
-        Updates.push_back({DominatorTree::Insert, BB, TransitionBB});
+        Updates.emplace_back(DominatorTree::Insert, BB, TransitionBB);
         for (BasicBlock *Successor : Successors) {
-          Updates.push_back({DominatorTree::Insert, TransitionBB, Successor});
-          Updates.push_back({DominatorTree::Delete, BB, Successor});
+          Updates.emplace_back(DominatorTree::Insert, TransitionBB, Successor);
+          Updates.emplace_back(DominatorTree::Delete, BB, Successor);
         }
 
         // Create a branch that will always branch to the transition block and
         // references DummyReturnBB.
         BB->getTerminator()->eraseFromParent();
         BranchInst::Create(TransitionBB, DummyReturnBB, BoolTrue, BB);
-        Updates.push_back({DominatorTree::Insert, BB, DummyReturnBB});
+        Updates.emplace_back(DominatorTree::Insert, BB, DummyReturnBB);
       }
       Changed = true;
     }
@@ -281,7 +281,7 @@ bool AMDGPUUnifyDivergentExitNodesImpl::run(Function &F, DominatorTree *DT,
         // Remove and delete the unreachable inst.
         BB->getTerminator()->eraseFromParent();
         BranchInst::Create(UnreachableBlock, BB);
-        Updates.push_back({DominatorTree::Insert, BB, UnreachableBlock});
+        Updates.emplace_back(DominatorTree::Insert, BB, UnreachableBlock);
       }
       Changed = true;
     }

llvm/lib/Target/AMDGPU/R600EmitClauseMarkers.cpp

@@ -133,20 +133,20 @@ class R600EmitClauseMarkers : public MachineFunctionPass {
       const std::pair<unsigned, unsigned> &BankLine = getAccessedBankLine(Sel);
       if (CachedConsts.empty()) {
         CachedConsts.push_back(BankLine);
-        UsedKCache.push_back(std::pair<unsigned, unsigned>(0, KCacheIndex));
+        UsedKCache.emplace_back(0, KCacheIndex);
         continue;
       }
       if (CachedConsts[0] == BankLine) {
-        UsedKCache.push_back(std::pair<unsigned, unsigned>(0, KCacheIndex));
+        UsedKCache.emplace_back(0, KCacheIndex);
         continue;
       }
       if (CachedConsts.size() == 1) {
         CachedConsts.push_back(BankLine);
-        UsedKCache.push_back(std::pair<unsigned, unsigned>(1, KCacheIndex));
+        UsedKCache.emplace_back(1, KCacheIndex);
         continue;
       }
       if (CachedConsts[1] == BankLine) {
-        UsedKCache.push_back(std::pair<unsigned, unsigned>(1, KCacheIndex));
+        UsedKCache.emplace_back(1, KCacheIndex);
         continue;
       }
       return false;

llvm/lib/Target/AMDGPU/R600InstrInfo.cpp

@@ -326,11 +326,11 @@ R600InstrInfo::ExtractSrcs(MachineInstr &MI,
     Register Reg = Src.first->getReg();
     int Index = RI.getEncodingValue(Reg) & 0xff;
     if (Reg == R600::OQAP) {
-      Result.push_back(std::pair(Index, 0U));
+      Result.emplace_back(Index, 0U);
     }
     if (PV.contains(Reg)) {
       // 255 is used to tells its a PS/PV reg
-      Result.push_back(std::pair(255, 0U));
+      Result.emplace_back(255, 0U);
       continue;
     }
     if (Index > 127) {
@@ -339,7 +339,7 @@ R600InstrInfo::ExtractSrcs(MachineInstr &MI,
       continue;
     }
     unsigned Chan = RI.getHWRegChan(Reg);
-    Result.push_back(std::pair(Index, Chan));
+    Result.emplace_back(Index, Chan);
   }
   for (; i < 3; ++i)
     Result.push_back(DummyPair);

llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp

@@ -58,7 +58,7 @@ class RegSeqInfo {
       MachineOperand &MO = Instr->getOperand(i);
       unsigned Chan = Instr->getOperand(i + 1).getImm();
       if (isImplicitlyDef(MRI, MO.getReg()))
-        UndefReg.push_back(Chan);
+        UndefReg.emplace_back(Chan);
       else
         RegToChan[MO.getReg()] = Chan;
     }
@@ -154,14 +154,12 @@ bool R600VectorRegMerger::tryMergeVector(const RegSeqInfo *Untouched,
     DenseMap<Register, unsigned>::const_iterator PosInUntouched =
         Untouched->RegToChan.find(It.first);
     if (PosInUntouched != Untouched->RegToChan.end()) {
-      Remap.push_back(
-          std::pair<unsigned, unsigned>(It.second, (*PosInUntouched).second));
+      Remap.emplace_back(It.second, (*PosInUntouched).second);
       continue;
     }
     if (CurrentUndexIdx >= Untouched->UndefReg.size())
       return false;
-    Remap.push_back(std::pair<unsigned, unsigned>(
-        It.second, Untouched->UndefReg[CurrentUndexIdx++]));
+    Remap.emplace_back(It.second, Untouched->UndefReg[CurrentUndexIdx++]);
   }
 
   return true;

llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp

@@ -237,7 +237,7 @@ bool SILowerSGPRSpills::spillCalleeSavedRegs(
         int JunkFI = MFI.CreateStackObject(TRI->getSpillSize(*RC),
                                            TRI->getSpillAlign(*RC), true);
 
-        CSI.push_back(CalleeSavedInfo(Reg, JunkFI));
+        CSI.emplace_back(Reg, JunkFI);
         CalleeSavedFIs.push_back(JunkFI);
       }
     }

llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

@@ -358,8 +358,7 @@ bool SIMachineFunctionInfo::allocateVirtualVGPRForSGPRSpills(
     LaneVGPR = SpillVGPRs.back();
   }
 
-  SGPRSpillsToVirtualVGPRLanes[FI].push_back(
-      SIRegisterInfo::SpilledReg(LaneVGPR, LaneIndex));
+  SGPRSpillsToVirtualVGPRLanes[FI].emplace_back(LaneVGPR, LaneIndex);
   return true;
 }
 
@@ -393,8 +392,7 @@ bool SIMachineFunctionInfo::allocatePhysicalVGPRForSGPRSpills(
     LaneVGPR = SpillPhysVGPRs.back();
   }
 
-  SGPRSpillsToPhysicalVGPRLanes[FI].push_back(
-      SIRegisterInfo::SpilledReg(LaneVGPR, LaneIndex));
+  SGPRSpillsToPhysicalVGPRLanes[FI].emplace_back(LaneVGPR, LaneIndex);
   return true;
 }
 

llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp

@@ -546,7 +546,7 @@ void SIScheduleBlock::addSucc(SIScheduleBlock *Succ,
   }
   if (Succ->isHighLatencyBlock())
     ++NumHighLatencySuccessors;
-  Succs.push_back(std::pair(Succ, Kind));
+  Succs.emplace_back(Succ, Kind);
 
   assert(none_of(Preds,
                  [=](SIScheduleBlock *P) { return SuccID == P->getID(); }) &&