44 * reserved.
55 * Copyright (c) 2020 Research Organization for Information Science
66 * and Technology (RIST). All rights reserved.
7+ * Copyright (c) 2021 Cisco Systems, Inc. All rights reserved.
78 * $COPYRIGHT$
89 *
910 * Additional copyrights may follow
2021#include "ompi_config.h"
2122
2223#include "opal/util/printf.h"
24+ #include "ompi/include/mpi_portable_platform.h"
2325
2426#include "ompi/constants.h"
2527#include "ompi/op/op.h"
@@ -35,6 +37,18 @@ static struct ompi_op_base_module_1_0_0_t *
3537 avx_component_op_query (struct ompi_op_t * op , int * priority );
3638static int avx_component_register (void );
3739
40+ static mca_base_var_enum_value_flag_t avx_support_flags [] = {
41+ { .flag = 0x001 , .string = "SSE" },
42+ { .flag = 0x002 , .string = "SSE2" },
43+ { .flag = 0x004 , .string = "SSE3" },
44+ { .flag = 0x008 , .string = "SSE4.1" },
45+ { .flag = 0x010 , .string = "AVX" },
46+ { .flag = 0x020 , .string = "AVX2" },
47+ { .flag = 0x100 , .string = "AVX512F" },
48+ { .flag = 0x200 , .string = "AVX512BW" },
49+ { .flag = 0 , .string = NULL },
50+ };
51+
3852/**
3953 * A slightly modified code from
4054 * https://software.intel.com/en-us/articles/how-to-detect-new-instruction-support-in-the-4th-generation-intel-core-processor-family
@@ -177,15 +191,38 @@ static int avx_component_close(void)
177191static int
178192avx_component_register (void )
179193{
180- int32_t requested_flags = mca_op_avx_component .flags = has_intel_AVX_features ();
194+ mca_op_avx_component .supported =
195+ mca_op_avx_component .flags = has_intel_AVX_features ();
196+
197+ // MCA var enum flag for conveniently seeing SSE/MMX/AVX support
198+ // values
199+ mca_base_var_enum_flag_t * new_enum_flag ;
200+ (void ) mca_base_var_enum_create_flag ("op_avx_support_flags" ,
201+ avx_support_flags , & new_enum_flag );
202+ (void ) mca_base_var_enum_register ("ompi" , "op" , "avx" , "support_flags" ,
203+ & new_enum_flag );
204+
205+ (void ) mca_base_component_var_register (& mca_op_avx_component .super .opc_version ,
206+ "capabilities" ,
207+ "Level of SSE/MMX/AVX support available in the current environment" ,
208+ MCA_BASE_VAR_TYPE_INT ,
209+ & (new_enum_flag -> super ), 0 , 0 ,
210+ OPAL_INFO_LVL_4 ,
211+ MCA_BASE_VAR_SCOPE_CONSTANT ,
212+ & mca_op_avx_component .supported );
213+
181214 (void ) mca_base_component_var_register (& mca_op_avx_component .super .opc_version ,
182215 "support" ,
183- "Level of SSE/MMX/AVX support to be used (combination of processor capabilities as follow SSE 0x01, SSE2 0x02, SSE3 0x04, SSE4.1 0x08, AVX 0x010, AVX2 0x020, AVX512F 0x100, AVX512BW 0x200) capped by the local architecture capabilities" ,
184- MCA_BASE_VAR_TYPE_INT , NULL , 0 , 0 ,
185- OPAL_INFO_LVL_6 ,
216+ "Level of SSE/MMX/AVX support to be used, capped by the local architecture capabilities" ,
217+ MCA_BASE_VAR_TYPE_INT ,
218+ & (new_enum_flag -> super ), 0 , 0 ,
219+ OPAL_INFO_LVL_4 ,
186220 MCA_BASE_VAR_SCOPE_LOCAL ,
187221 & mca_op_avx_component .flags );
188- mca_op_avx_component .flags &= requested_flags ;
222+ OBJ_RELEASE (new_enum_flag );
223+
224+ mca_op_avx_component .flags &= mca_op_avx_component .supported ;
225+
189226 return OMPI_SUCCESS ;
190227}
191228
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