|
14 | 14 | * Copyright (c) 2010 ARM ltd. All rights reserved. |
15 | 15 | * Copyright (c) 2016-2018 Los Alamos National Security, LLC. All rights |
16 | 16 | * reserved. |
| 17 | + * Copyright (c) 2021 Triad National Security, LLC. All rights reserved. |
| 18 | + * Copyright (c) 2021 Google, LLC. All rights reserved. |
17 | 19 | * $COPYRIGHT$ |
18 | 20 | * |
19 | 21 | * Additional copyrights may follow |
20 | 22 | * |
21 | 23 | * $HEADER$ |
22 | 24 | */ |
23 | 25 |
|
| 26 | +#include "atomic_llsc.h" |
| 27 | + |
24 | 28 | #if !defined(OPAL_SYS_ARCH_ATOMIC_H) |
25 | 29 |
|
26 | 30 | #define OPAL_SYS_ARCH_ATOMIC_H 1 |
27 | 31 |
|
28 | 32 | #if OPAL_GCC_INLINE_ASSEMBLY |
29 | 33 |
|
30 | 34 | #define OPAL_HAVE_ATOMIC_MEM_BARRIER 1 |
31 | | -#define OPAL_HAVE_ATOMIC_LLSC_32 1 |
32 | 35 | #define OPAL_HAVE_ATOMIC_COMPARE_EXCHANGE_32 1 |
33 | 36 | #define OPAL_HAVE_ATOMIC_SWAP_32 1 |
34 | 37 | #define OPAL_HAVE_ATOMIC_MATH_32 1 |
35 | 38 | #define OPAL_HAVE_ATOMIC_COMPARE_EXCHANGE_64 1 |
36 | 39 | #define OPAL_HAVE_ATOMIC_SWAP_64 1 |
37 | | -#define OPAL_HAVE_ATOMIC_LLSC_64 1 |
38 | 40 | #define OPAL_HAVE_ATOMIC_ADD_32 1 |
39 | 41 | #define OPAL_HAVE_ATOMIC_AND_32 1 |
40 | 42 | #define OPAL_HAVE_ATOMIC_OR_32 1 |
@@ -162,32 +164,6 @@ static inline bool opal_atomic_compare_exchange_strong_rel_32 (opal_atomic_int32 |
162 | 164 | return ret; |
163 | 165 | } |
164 | 166 |
|
165 | | -#define opal_atomic_ll_32(addr, ret) \ |
166 | | - do { \ |
167 | | - opal_atomic_int32_t *_addr = (addr); \ |
168 | | - int32_t _ret; \ |
169 | | - \ |
170 | | - __asm__ __volatile__ ("ldaxr %w0, [%1] \n" \ |
171 | | - : "=&r" (_ret) \ |
172 | | - : "r" (_addr)); \ |
173 | | - \ |
174 | | - ret = (typeof(ret)) _ret; \ |
175 | | - } while (0) |
176 | | - |
177 | | -#define opal_atomic_sc_32(addr, newval, ret) \ |
178 | | - do { \ |
179 | | - opal_atomic_int32_t *_addr = (addr); \ |
180 | | - int32_t _newval = (int32_t) newval; \ |
181 | | - int _ret; \ |
182 | | - \ |
183 | | - __asm__ __volatile__ ("stlxr %w0, %w2, [%1] \n" \ |
184 | | - : "=&r" (_ret) \ |
185 | | - : "r" (_addr), "r" (_newval) \ |
186 | | - : "cc", "memory"); \ |
187 | | - \ |
188 | | - ret = (_ret == 0); \ |
189 | | - } while (0) |
190 | | - |
191 | 167 | static inline bool opal_atomic_compare_exchange_strong_64 (opal_atomic_int64_t *addr, int64_t *oldval, int64_t newval) |
192 | 168 | { |
193 | 169 | int64_t prev; |
@@ -272,32 +248,6 @@ static inline bool opal_atomic_compare_exchange_strong_rel_64 (opal_atomic_int64 |
272 | 248 | return ret; |
273 | 249 | } |
274 | 250 |
|
275 | | -#define opal_atomic_ll_64(addr, ret) \ |
276 | | - do { \ |
277 | | - opal_atomic_int64_t *_addr = (addr); \ |
278 | | - int64_t _ret; \ |
279 | | - \ |
280 | | - __asm__ __volatile__ ("ldaxr %0, [%1] \n" \ |
281 | | - : "=&r" (_ret) \ |
282 | | - : "r" (_addr)); \ |
283 | | - \ |
284 | | - ret = (typeof(ret)) _ret; \ |
285 | | - } while (0) |
286 | | - |
287 | | -#define opal_atomic_sc_64(addr, newval, ret) \ |
288 | | - do { \ |
289 | | - opal_atomic_int64_t *_addr = (addr); \ |
290 | | - int64_t _newval = (int64_t) newval; \ |
291 | | - int _ret; \ |
292 | | - \ |
293 | | - __asm__ __volatile__ ("stlxr %w0, %2, [%1] \n" \ |
294 | | - : "=&r" (_ret) \ |
295 | | - : "r" (_addr), "r" (_newval) \ |
296 | | - : "cc", "memory"); \ |
297 | | - \ |
298 | | - ret = (_ret == 0); \ |
299 | | - } while (0) |
300 | | - |
301 | 251 | #define OPAL_ASM_MAKE_ATOMIC(type, bits, name, inst, reg) \ |
302 | 252 | static inline type opal_atomic_fetch_ ## name ## _ ## bits (opal_atomic_ ## type *addr, type value) \ |
303 | 253 | { \ |
|
0 commit comments