[WIP] Implement a VHDL backend

src/vhdl_backend.cc

@@ -540,6 +540,7 @@ void dump_memory_types(std::ostream &f, std::string indent, RTLIL::Memory *memor
 		range_str.c_str());
 }
 
+// TODO: document results of gen_signed, gen_unsigned
 void dump_cell_expr_port(std::ostream &f, RTLIL::Cell *cell, std::string port, bool gen_signed = true, bool gen_unsigned = false)
 { // PORTING NEEDS TESTING
 	SigSpec signal_spec = cell->getPort("\\" + port);
@@ -844,6 +845,8 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 	}
 
 	// TODO: port $eqx and $nex ("=" and "/=" return BIT, not STD_LOGIC)
+	// TODO: ?= and friends may be a VHDL-2008 addition?
+	// TODO: unported elements
 	// TODO: use "?<" instead of "<" (and analogous) for others?
 	HANDLE_BINOP(ID($lt),  "<",  true)
 	HANDLE_BINOP(ID($le),  "<=", true)
@@ -859,7 +862,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 	HANDLE_BINOP(ID($mul), "*",   true)
 	HANDLE_BINOP(ID($div), "/",   true)
 	HANDLE_BINOP(ID($mod), "mod", true)
-	HANDLE_BINOP(ID($pow), "**",  true) // unported
+	HANDLE_BINOP(ID($pow), "**",  true)
 
 	if (cell->type == ID($logic_not)) {
 		// TODO: use VHDL-93 compliant syntax
@@ -941,7 +944,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 	}
 
 	if (cell->type == ID($modfloor))
-	{ // unported for now
+	{ // unported for now (rem?)
 		// wire truncated = $signed(A) % $signed(B);
 		// assign Y = (A[-1] == B[-1]) || truncated == 0 ? truncated : $signed(B) + $signed(truncated);
 
@@ -1703,25 +1706,51 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		std::stringstream a_sstream; // Not actually arbitrary haha
 		string en_str;
 		string a_str; // [A]rticle of interest
-		dump_sigspec(en_sstream, cell->getPort(ID::EN));
-		dump_sigspec(a_sstream, cell->getPort(ID::A));
+		SigSpec en_sigspec = cell->getPort(ID::EN);
+		dump_sigspec(en_sstream, en_sigspec);
+		/*
+		 * en_sigspec should be exactly one bit wide
+		 * Use this to skip the hypothesis portion of the implication
+		 * (A false hypothesis causes the property to be a tautology)
+		 */
+		bool en_const_on = en_sigspec.is_fully_ones();
 		en_str = en_sstream.str();
+
+		dump_sigspec(a_sstream, cell->getPort(ID::A));
 		a_str = a_sstream.str();
+		// TODO: special handling for asserts of x->'1'?
 		if (cell->type == ID($assert)) {
-			f << stringf("%s" "assert (not %s) or %s;", indent.c_str(),
-					en_str.c_str(),a_str.c_str());
-			f << stringf(" -- %s -> %s\n", en_str.c_str(), a_str.c_str());
+			if (en_const_on) {
+				f << stringf("%s" "assert %s;\n", indent.c_str(),
+						a_str.c_str());
+			} else {
+				f << stringf("%s" "assert (not %s) or %s;", indent.c_str(),
+						en_str.c_str(), a_str.c_str());
+				f << stringf(" -- %s -> %s\n", en_str.c_str(), a_str.c_str());
+			}
 		} else {
-			f << stringf("%s" "-- psl %s ", indent.c_str(), cell->type.c_str()+1);
+			f << stringf("%s", indent.c_str());
+			if (!std08 && cell->type != ID($assert)) {
+				// PSL comment that GHDL interprets with -fpsl
+				f << stringf("-- psl ");
+			}
+			f << stringf("%s ", cell->type.c_str()+1);
+			const char* property_impl_str;
+			if (en_const_on) {
+				property_impl_str = a_str.c_str();
+			} else {
+				property_impl_str = stringf("%s -> %s",
+						en_str.c_str(), a_str.c_str()).c_str();
+			}
 			if (cell->type != ID($cover)) {
-				f << stringf("always (%s -> %s);\n",
-						en_str.c_str(), a_str.c_str());
+				f << stringf("always (%s);\n",
+						property_impl_str);
 			} else {
 				/*
 				 * PSL cover statements require a Sequence (PSL 2005 7.1.6)
 				 * Construct a one-long sequence as a Braced SERE
 				 */
-				f << stringf("{%s -> %s};\n", en_str.c_str(), a_str.c_str());
+				f << stringf("{%s};\n", property_impl_str);
 			}
 		}
 		return true;
@@ -2126,6 +2155,7 @@ void write_header_imports(std::ostream &f, std::string indent)
 {
 	f << indent << "library IEEE;\n";
 	f << indent << "use IEEE.STD_LOGIC_1164.ALL;\n";
+	// Could scan for arithmetic-type cells, but this is too cumbersome
 	f << indent << "use IEEE.NUMERIC_STD.ALL;\n";
 	if (extmem) {
 		f << indent << "\nuse STD.TEXTIO.ALL\n";