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arm64: dts: s32g: add common 'S32G-EVB' and 'S32G-RDB' board support
JIRA: https://issues.redhat.com/browse/RHEL-116642 commit 81a97af Author: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> Date: Mon Jan 13 13:05:11 2025 +0200 arm64: dts: s32g: add common 'S32G-EVB' and 'S32G-RDB' board support Create common part, s32gxxa-evb.dtsi and s32gxxa-rdb.dtsi, for S32G2/S32G3 RDB2\3 and EVB G2/G3 boards to avoid copy duplicate part in boards dts file. Prepare to add other modules such as FlexCAN, DSPI easily in the future. Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> Reviewed-by: Matthias Brugger <mbrugger@suse.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Jared Kangas <jkangas@redhat.com>
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‎arch/arm64/boot/dts/freescale/s32g274a-evb.dts‎

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/dts-v1/;
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#include "s32g2.dtsi"
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#include "s32gxxxa-evb.dtsi"
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/ {
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model = "NXP S32G2 Evaluation Board (S32G-VNP-EVB)";

‎arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts‎

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/dts-v1/;
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#include "s32g2.dtsi"
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#include "s32gxxxa-rdb.dtsi"
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/ {
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model = "NXP S32G2 Reference Design Board 2 (S32G-VNP-RDB2)";

‎arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts‎

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/dts-v1/;
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#include "s32g3.dtsi"
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#include "s32gxxxa-rdb.dtsi"
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/ {
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model = "NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)";

‎arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi‎

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright 2024 NXP
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*
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* Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
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* Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
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* Larisa Grigore <larisa.grigore@nxp.com>
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*/
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&pinctrl {
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i2c0_pins: i2c0-pins {
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i2c0-grp0 {
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pinmux = <0x101>, <0x111>;
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drive-open-drain;
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output-enable;
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input-enable;
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slew-rate = <133>;
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};
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i2c0-grp1 {
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pinmux = <0x2352>, <0x2362>;
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};
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};
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i2c0_gpio_pins: i2c0-gpio-pins {
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i2c0-gpio-grp0 {
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pinmux = <0x100>, <0x110>;
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drive-open-drain;
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output-enable;
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input-enable;
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slew-rate = <133>;
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};
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i2c0-gpio-grp1 {
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pinmux = <0x2350>, <0x2360>;
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};
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};
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i2c1_pins: i2c1-pins {
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i2c1-grp0 {
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pinmux = <0x131>, <0x141>;
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drive-open-drain;
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output-enable;
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input-enable;
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slew-rate = <133>;
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};
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i2c1-grp1 {
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pinmux = <0x2cd2>, <0x2ce2>;
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};
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};
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i2c1_gpio_pins: i2c1-gpio-pins {
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i2c1-gpio-grp0 {
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pinmux = <0x130>, <0x140>;
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drive-open-drain;
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output-enable;
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input-enable;
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slew-rate = <133>;
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};
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i2c1-gpio-grp1 {
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pinmux = <0x2cd0>, <0x2ce0>;
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};
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};
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i2c2_pins: i2c2-pins {
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i2c2-grp0 {
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pinmux = <0x151>, <0x161>;
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drive-open-drain;
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output-enable;
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input-enable;
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slew-rate = <133>;
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};
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i2c2-grp1 {
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pinmux = <0x2cf2>, <0x2d02>;
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};
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};
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i2c2_gpio_pins: i2c2-gpio-pins {
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i2c2-gpio-grp0 {
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pinmux = <0x150>, <0x160>;
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drive-open-drain;
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output-enable;
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input-enable;
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slew-rate = <133>;
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};
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i2c2-gpio-grp1 {
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pinmux = <0x2cf0>, <0x2d00>;
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};
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};
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i2c4_pins: i2c4-pins {
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i2c4-grp0 {
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pinmux = <0x211>, <0x222>;
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drive-open-drain;
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output-enable;
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input-enable;
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slew-rate = <133>;
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};
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i2c4-grp1 {
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pinmux = <0x2d43>, <0x2d33>;
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};
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};
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i2c4_gpio_pins: i2c4-gpio-pins {
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i2c4-gpio-grp0 {
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pinmux = <0x210>, <0x220>;
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drive-open-drain;
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output-enable;
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input-enable;
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slew-rate = <133>;
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};
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i2c4-gpio-grp1 {
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pinmux = <0x2d40>, <0x2d30>;
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};
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};
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};
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&i2c0 {
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-1 = <&i2c0_gpio_pins>;
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status = "okay";
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};
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&i2c1 {
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-1 = <&i2c1_gpio_pins>;
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status = "okay";
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};
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&i2c2 {
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&i2c2_pins>;
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pinctrl-1 = <&i2c2_gpio_pins>;
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status = "okay";
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};
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&i2c4 {
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&i2c4_pins>;
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pinctrl-1 = <&i2c4_gpio_pins>;
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status = "okay";
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};

‎arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi‎

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright 2024 NXP
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*
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* Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
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* Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
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* Larisa Grigore <larisa.grigore@nxp.com>
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*/
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&pinctrl {
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i2c0_pins: i2c0-pins {
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i2c0-grp0 {
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pinmux = <0x1f2>, <0x201>;
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drive-open-drain;
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output-enable;
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input-enable;
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slew-rate = <133>;
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};
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i2c0-grp1 {
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pinmux = <0x2353>, <0x2363>;
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};
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};
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i2c0_gpio_pins: i2c0-gpio-pins {
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i2c0-gpio-grp0 {
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pinmux = <0x1f0>, <0x200>;
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drive-open-drain;
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output-enable;
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input-enable;
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slew-rate = <133>;
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};
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i2c0-gpio-grp1 {
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pinmux = <0x2350>, <0x2360>;
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};
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};
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i2c2_pins: i2c2-pins {
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i2c2-grp0 {
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pinmux = <0x151>, <0x161>;
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drive-open-drain;
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output-enable;
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input-enable;
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slew-rate = <133>;
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};
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i2c2-grp1 {
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pinmux = <0x2cf2>, <0x2d02>;
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};
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};
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i2c2_gpio_pins: i2c2-gpio-pins {
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i2c2-gpio-grp0 {
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pinmux = <0x2cf0>, <0x2d00>;
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};
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i2c2-gpio-grp1 {
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pinmux = <0x150>, <0x160>;
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drive-open-drain;
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output-enable;
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input-enable;
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slew-rate = <133>;
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};
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};
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i2c4_pins: i2c4-pins {
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i2c4-grp0 {
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pinmux = <0x211>, <0x222>;
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drive-open-drain;
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output-enable;
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input-enable;
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slew-rate = <133>;
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};
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i2c4-grp1 {
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pinmux = <0x2d43>, <0x2d33>;
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};
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};
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i2c4_gpio_pins: i2c4-gpio-pins {
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i2c4-gpio-grp0 {
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pinmux = <0x210>, <0x220>;
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drive-open-drain;
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output-enable;
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input-enable;
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slew-rate = <133>;
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};
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i2c4-gpio-grp1 {
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pinmux = <0x2d40>, <0x2d30>;
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};
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};
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};
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&i2c0 {
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-1 = <&i2c0_gpio_pins>;
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status = "okay";
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pcal6524: gpio-expander@22 {
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compatible = "nxp,pcal6524";
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reg = <0x22>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&i2c2 {
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&i2c2_pins>;
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pinctrl-1 = <&i2c2_gpio_pins>;
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status = "okay";
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};
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&i2c4 {
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&i2c4_pins>;
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pinctrl-1 = <&i2c4_gpio_pins>;
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status = "okay";
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};

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