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Merge branches 'clk-parent', 'clk-renesas', 'clk-mediatek' and 'clk-cleanup' into clk-next
* clk-parent: clk: check for disabled clock-provider in of_clk_get_hw_from_clkspec() * clk-renesas: (24 commits) clk: renesas: r9a09g047: Add clock and reset signals for the TSU IP clk: renesas: rzv2h: Adjust for CPG_BUS_m_MSTOP starting from m = 1 clk: renesas: r7s9210: Distinguish clocks by clock type clk: renesas: rzg2l: Remove unneeded nullify checks clk: renesas: cpg-mssr: Remove obsolete nullify check clk: renesas: r9a09g057: Add entries for the DMACs clk: renesas: r9a09g047: Add CANFD clocks and resets clk: renesas: r9a09g047: Add CRU0 clocks and resets clk: renesas: rzv2h: Update error message clk: renesas: rzg2l: Update error message clk: renesas: r9a09g047: Add ICU clock/reset clk: renesas: r9a07g043: Fix HP clock source for RZ/Five clk: renesas: r9a09g047: Add SDHI clocks/resets clk: renesas: r8a779h0: Add VSPX clock clk: renesas: r8a779h0: Add FCPVX clock clk: renesas: r8a08g045: Check the source of the CPU PLL settings clk: renesas: r9a09g047: Add WDT clocks and resets clk: renesas: r8a779h0: Add ISP core clocks clk: renesas: r8a779g0: Add ISP core clocks clk: renesas: r8a779a0: Add ISP core clocks ... * clk-mediatek: clk: mediatek: Add SMI LARBs reset for MT8188 dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188 clk: mediatek: mt8188-vdo1: Add VDO1_DPI1_HDMI clock for hdmitx dt-bindings: clock: mediatek,mt8188: Add VDO1_DPI1_HDMI clock * clk-cleanup: dt-bindings: clocks: atmel,at91rm9200-pmc: add missing compatibles clk: davinci: remove support for da830 dt-bindings: clock: ti: Convert ti-clkctrl.txt to json-schema clk: mmp: Fix NULL vs IS_ERR() check clk: Print an error when clk registration fails clk: Correct the data types of the variables in clk_calc_new_rates clk: imgtec: use %pe for better readability of errors while printing clk: stm32f4: fix an uninitialized variable clk: keystone: syscon-clk: Do not use syscon helper to build regmap
4 parents b20150d + fca77a6 + 0ca0dc8 + 86484e0 commit 316f4b9

35 files changed

+460
-380
lines changed

‎Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -34,6 +34,8 @@ properties:
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- enum:
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- atmel,at91rm9200-pmc
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- atmel,at91sam9260-pmc
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- atmel,at91sam9261-pmc
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- atmel,at91sam9263-pmc
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- atmel,at91sam9g45-pmc
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- atmel,at91sam9n12-pmc
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- atmel,at91sam9rl-pmc
@@ -111,6 +113,8 @@ allOf:
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enum:
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- atmel,at91rm9200-pmc
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- atmel,at91sam9260-pmc
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- atmel,at91sam9261-pmc
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- atmel,at91sam9263-pmc
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- atmel,at91sam9g20-pmc
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then:
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properties:

‎Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -57,6 +57,27 @@ required:
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- reg
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- '#clock-cells'
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- mediatek,mt8188-camsys-rawa
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- mediatek,mt8188-camsys-rawb
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- mediatek,mt8188-camsys-yuva
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- mediatek,mt8188-camsys-yuvb
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- mediatek,mt8188-imgsys-wpe1
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- mediatek,mt8188-imgsys-wpe2
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- mediatek,mt8188-imgsys-wpe3
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- mediatek,mt8188-imgsys1-dip-nr
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- mediatek,mt8188-imgsys1-dip-top
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- mediatek,mt8188-ipesys
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then:
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required:
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- '#reset-cells'
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additionalProperties: false
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examples:

‎Documentation/devicetree/bindings/clock/ti,clkctrl.yaml‎

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@@ -0,0 +1,65 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/ti,clkctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Texas Instruments clkctrl clock
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maintainers:
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- Tony Lindgren <tony@atomide.com>
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- Andreas Kemnade <andreas@kemnade.info>
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description: |
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Texas Instruments SoCs can have a clkctrl clock controller for each
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interconnect target module. The clkctrl clock controller manages functional
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and interface clocks for each module. Each clkctrl controller can also
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gate one or more optional functional clocks for a module, and can have one
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or more clock muxes. There is a clkctrl clock controller typically for each
19+
interconnect target module on omap4 and later variants.
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The clock consumers can specify the index of the clkctrl clock using
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the hardware offset from the clkctrl instance register space. The optional
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clocks can be specified by clkctrl hardware offset and the index of the
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optional clock.
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properties:
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compatible:
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enum:
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- ti,clkctrl
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- ti,clkctrl-l4-cfg
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- ti,clkctrl-l4-per
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- ti,clkctrl-l4-secure
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- ti,clkctrl-l4-wkup
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"#clock-cells":
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const: 2
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clock-output-names:
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maxItems: 1
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reg:
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minItems: 1
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maxItems: 8 # arbitrary, should be enough
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required:
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- compatible
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- "#clock-cells"
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- clock-output-names
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- reg
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additionalProperties: false
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examples:
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- |
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bus {
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#address-cells = <1>;
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#size-cells = <1>;
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clock@20 {
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compatible = "ti,clkctrl";
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clock-output-names = "l4_per";
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reg = <0x20 0x1b0>;
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#clock-cells = <2>;
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};
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};

‎Documentation/devicetree/bindings/clock/ti-clkctrl.txt‎

Lines changed: 0 additions & 63 deletions
This file was deleted.

‎drivers/clk/clk-stm32f4.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -888,7 +888,6 @@ static int __init stm32f4_pll_ssc_parse_dt(struct device_node *np,
888888
struct stm32f4_pll_ssc *conf)
889889
{
890890
int ret;
891-
const char *s;
892891

893892
if (!conf)
894893
return -EINVAL;
@@ -916,7 +915,8 @@ static int __init stm32f4_pll_ssc_parse_dt(struct device_node *np,
916915
conf->mod_type = ret;
917916

918917
pr_debug("%pOF: SSCG settings: mod_freq: %d, mod_depth: %d mod_method: %s [%d]\n",
919-
np, conf->mod_freq, conf->mod_depth, s, conf->mod_type);
918+
np, conf->mod_freq, conf->mod_depth,
919+
stm32f4_ssc_mod_methods[ret], conf->mod_type);
920920

921921
return 0;
922922
}

‎drivers/clk/clk.c‎

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Original file line numberDiff line numberDiff line change
@@ -2283,7 +2283,7 @@ static struct clk_core *clk_calc_new_rates(struct clk_core *core,
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unsigned long min_rate;
22842284
unsigned long max_rate;
22852285
int p_index = 0;
2286-
long ret;
2286+
int ret;
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22882288
/* sanity */
22892289
if (IS_ERR_OR_NULL(core))
@@ -4397,6 +4397,13 @@ __clk_register(struct device *dev, struct device_node *np, struct clk_hw *hw)
43974397
fail_name:
43984398
kref_put(&core->ref, __clk_release);
43994399
fail_out:
4400+
if (dev) {
4401+
dev_err_probe(dev, ret, "failed to register clk '%s' (%pS)\n",
4402+
init->name, hw);
4403+
} else {
4404+
pr_err("%pOF: error %pe: failed to register clk '%s' (%pS)\n",
4405+
np, ERR_PTR(ret), init->name, hw);
4406+
}
44004407
return ERR_PTR(ret);
44014408
}
44024409

‎drivers/clk/davinci/Makefile‎

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@@ -4,10 +4,8 @@ ifeq ($(CONFIG_COMMON_CLK), y)
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obj-$(CONFIG_ARCH_DAVINCI_DA8XX) += da8xx-cfgchip.o
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obj-y += pll.o
7-
obj-$(CONFIG_ARCH_DAVINCI_DA830) += pll-da830.o
87
obj-$(CONFIG_ARCH_DAVINCI_DA850) += pll-da850.o
98

109
obj-y += psc.o
11-
obj-$(CONFIG_ARCH_DAVINCI_DA830) += psc-da830.o
1210
obj-$(CONFIG_ARCH_DAVINCI_DA850) += psc-da850.o
1311
endif

‎drivers/clk/davinci/pll-da830.c‎

Lines changed: 0 additions & 71 deletions
This file was deleted.

‎drivers/clk/davinci/pll.c‎

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Original file line numberDiff line numberDiff line change
@@ -840,25 +840,16 @@ int of_davinci_pll_init(struct device *dev, struct device_node *node,
840840
}
841841

842842
/* needed in early boot for clocksource/clockevent */
843-
#ifdef CONFIG_ARCH_DAVINCI_DA850
844843
CLK_OF_DECLARE(da850_pll0, "ti,da850-pll0", of_da850_pll0_init);
845-
#endif
846844

847845
static const struct of_device_id davinci_pll_of_match[] = {
848-
#ifdef CONFIG_ARCH_DAVINCI_DA850
849846
{ .compatible = "ti,da850-pll1", .data = of_da850_pll1_init },
850-
#endif
851847
{ }
852848
};
853849

854850
static const struct platform_device_id davinci_pll_id_table[] = {
855-
#ifdef CONFIG_ARCH_DAVINCI_DA830
856-
{ .name = "da830-pll", .driver_data = (kernel_ulong_t)da830_pll_init },
857-
#endif
858-
#ifdef CONFIG_ARCH_DAVINCI_DA850
859851
{ .name = "da850-pll0", .driver_data = (kernel_ulong_t)da850_pll0_init },
860852
{ .name = "da850-pll1", .driver_data = (kernel_ulong_t)da850_pll1_init },
861-
#endif
862853
{ }
863854
};
864855

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