Add I2C and improve FPU for stm32f3 core

Author: mathk

core/src/cpus/cortex_m/m4.zig

@@ -84,6 +84,23 @@ pub const SystemControlBlock = extern struct {
     BFAR: u32,
     /// Auxilary Feature Register.
     AFSR: u32,
+    reserved0: [18]u32,
+    CPACR: mmio.Mmio(packed struct(u32) {
+        reserved0: u20,
+        CP10: Privilege,
+        CP11: Privilege,
+        reserved1: u8,
+
+        pub const Privilege = enum(u2) {
+            /// Access denied. Any attempted access generates a NOCP UsageFault.
+            access_denied = 0b00,
+            /// Privileged access only. An unprivileged access generates a NOCP UsageFault.
+            priviledged_access_only = 0b01,
+            reserved = 0b10,
+            /// Full access.
+            full_access = 0b11,
+        };
+    }),
 };
 
 pub const NestedVectorInterruptController = extern struct {
@@ -187,3 +204,39 @@ pub const MemoryProtectionUnit = extern struct {
         reserved2: u3 = 0,
     });
 };
+
+pub const FloatingPointUnit = extern struct {
+    FPCCR: mmio.Mmio(packed struct(u32) {
+        LSPACT: u1,
+        USER: u1,
+        reserved0: u1 = 0,
+        THREAD: u1,
+        HFRDY: u1,
+        MMRDY: u1,
+        BFRDY: u1,
+        reserved1: u1 = 0,
+        MONRDY: u1,
+        reserved2: u21 = 0,
+        /// Automatic state preservation enable. Enables lazy context save of
+        /// floating-point state. The possible values of this bit are:
+        /// 0 = Disable automatic lazy context save.
+        /// 1 = Enable automatic lazy state preservation for floating-point
+        /// context.
+        ///
+        /// Writes to this bit from Non-secure state are ignored if LSPENS is
+        /// set to one.
+        LSPEN: u1,
+        /// Automatic state preservation enable. Enables CONTROL.FPCA setting
+        /// on execution of a floating-point instruction. This results in
+        /// automatic hardware state preservation and restoration, for
+        /// floating-point context, on exception entry and exit. The possible
+        /// values of this bit are:
+        /// 1 = Enable CONTROL.FPCA setting on execution of a floating-point
+        /// instruction.
+        /// 0 = Disable CONTROL.FPCA setting on execution of a
+        /// floating-point instruction.
+        ASPEN: u1,
+    }),
+    FPCAR: u32,
+    FPDSCR: u32,
+};

port/stmicro/stm32/src/boards/STM32F3DISCOVERY.zig

@@ -1,3 +1,5 @@
+const std = @import("std");
+
 pub const microzig = @import("microzig");
 pub const hal = microzig.hal;
 pub const rcc = hal.rcc;
@@ -27,7 +29,7 @@ pub const pin_map = .{
 pub fn init() void {
     hal.enable_fpu();
     rcc.enable_hse(8_000_000);
-    rcc.enable_pll(.HSE, .Div1, .Mul6) catch {
+    rcc.enable_pll(.HSE, .Div1, .Mul5) catch {
         @panic("PLL faile to enable");
     };
     rcc.select_pll_for_sysclk() catch {