Initial setup for RCC.

Author: mathk

port/stmicro/stm32/src/boards/STM32F3DISCOVERY.zig

@@ -1,4 +1,7 @@
 pub const microzig = @import("microzig");
+pub const hal = microzig.hal;
+pub const rcc = hal.rcc;
+pub const pins = hal.pins;
 
 pub const pin_map = .{
     // circle of LEDs, connected to GPIOE bits 8..15
@@ -20,3 +23,26 @@ pub const pin_map = .{
     // W green
     .LD6 = "PE15",
 };
+
+pub fn init() void {
+    hal.enable_fpu();
+    rcc.enable_hse(8_000_000);
+    rcc.enable_pll(.HSE, .Div1, .Mul6) catch {
+        @panic("PLL faile to enable");
+    };
+    rcc.select_pll_for_sysclk() catch {
+        @panic("Faile to select sysclk");
+    };
+}
+
+// Init should come first or the baud_rate would be too fast for the default HSI.
+pub fn init_log() void {
+    _ = (pins.GlobalConfiguration{
+        .GPIOC = .{
+            .PIN4 = .{ .mode = .{ .alternate_function = .{ .afr = .AF7 } } },
+            .PIN5 = .{ .mode = .{ .alternate_function = .{ .afr = .AF7 } } },
+        },
+    }).apply();
+    const uart = try microzig.hal.uart.Uart(.UART1).init(.{ .baud_rate = 115200 });
+    microzig.hal.uart.init_logger(&uart);
+}

port/stmicro/stm32/src/hals/STM32F303.zig

@@ -49,6 +49,8 @@ const runtime_safety = std.debug.runtime_safety;
 const microzig = @import("microzig");
 pub const gpio = @import("STM32F303/gpio.zig");
 pub const uart = @import("STM32F303/uart.zig");
+pub const rcc = @import("STM32F303/rcc.zig");
+pub const i2c = @import("STM32F303/i2c.zig");
 
 const SPI1 = microzig.peripherals.SPI1;
 const RCC = microzig.chip.peripherals.RCC;
@@ -92,6 +94,52 @@ fn debug_print(comptime format: []const u8, args: anytype) void {
     }
 }
 
+// Those are missing from the cortex_m4
+// Maybe a specificity from STM that have those FPU unit.
+const CPACP = microzig.mmio.Mmio(packed struct(u32) {
+    reserved1: u20 = 0,
+    CP10: u2,
+    CP11: u2,
+    reserved2: u8 = 0,
+});
+
+pub const FPCCR = microzig.mmio.Mmio(packed struct(u32) {
+    LSPACT: u1,
+    USER: u1,
+    S: u1,
+    THREAD: u1,
+    HFRDY: u1,
+    MMRDY: u1,
+    BFRDY: u1,
+    SFRDY: u1,
+    MONRDY: u1,
+    SPLIMVIOL: u1,
+    UFRDY: u1,
+    reserved0: u15 = 0,
+    TS: u1,
+    CLRONRETS: u1,
+    CLRONRET: u1,
+    LSPENS: u1,
+    LSPEN: u1,
+    ASPEN: u1,
+});
+
+pub const missing_peripherals = .{
+    .cpacr = @as(*volatile CPACP, @ptrFromInt(0xE000ED88)),
+    .fpccr = @as(*volatile FPCCR, @ptrFromInt(0xE000EF34)),
+};
+
+pub fn enable_fpu() void {
+    missing_peripherals.cpacr.modify(.{
+        .CP10 = 0b11,
+        .CP11 = 0b11,
+    });
+    missing_peripherals.fpccr.modify(.{
+        .ASPEN = 1,
+        .LSPEN = 1,
+    });
+}
+
 /// This implementation does not use AUTOEND=1
 pub fn I2CController(comptime index: usize, comptime source_pins: microzig.i2c.Pins) type {
     if (!(index == 1)) @compileError("TODO: only I2C1 is currently supported");

port/stmicro/stm32/src/hals/STM32F303/pins.zig

@@ -57,6 +57,14 @@ pub const OutputGPIO = struct {
         }
     }
 
+    pub inline fn low(self: @This()) void {
+        self.put(0);
+    }
+
+    pub inline fn high(self: @This()) void {
+        self.put(1);
+    }
+
     pub inline fn toggle(self: @This()) void {
         var port = self.pin.get_port();
         port.ODR.raw ^= self.pin.mask();

port/stmicro/stm32/src/hals/STM32F303/rcc.zig

@@ -1,13 +1,108 @@
-pub const Clock = struct {
-    sys_clk: u32,
-    ahb: u32,
-    apb1: u32,
-    apb2: u32,
+const microzig = @import("microzig");
+const RCC = microzig.chip.peripherals.RCC;
+const GPIOF = microzig.chip.peripherals.GPIOF;
+const FLASH = microzig.chip.peripherals.FLASH;
+const PREDIV = microzig.chip.types.peripherals.rcc_f3v1.PREDIV;
+const PLLMUL = microzig.chip.types.peripherals.rcc_f3v1.PLLMUL;
+
+pub const ClockName = enum {
+    HSE,
+    HSI,
+    PLLCLK,
+    SYSCLK,
+
+    fn is_for_pll(self: @This()) bool {
+        return self == .HSE or self == .HSI;
+    }
+
+    fn is_for_sysclk(self: @This()) bool {
+        return self != .SYSCLK;
+    }
+};
+
+pub const RccErrorConfig = error{
+    WrongClockSource,
+    SourceClockNotInitialized,
+    OutputPllTooHigh,
+    PllMustBeEnableFirst,
 };
 
-pub var current_clock: Clock = .{
-    .sys_clk = 8_000_000,
-    .ahb = 8_000_000,
-    .apb1 = 8_000_000,
-    .apb2 = 8_000_000,
+pub const Clock = struct {
+    sys_clk: u32 = 8_000_000,
+    h_clk: u32 = 8_000_000,
+    p1_clk: u32 = 8_000_000,
+    p2_clk: u32 = 8_000_000,
+    hse: u32 = 0,
+    hsi: u32 = 8_000_000,
+    pllout: u32 = 0,
+    usart1_clk: u32 = 8_000_000,
 };
+
+pub var current_clock: Clock = .{};
+
+pub fn enable_pll(comptime source: ClockName, div: PREDIV, mul: PLLMUL) RccErrorConfig!void {
+    if (!source.is_for_pll()) {
+        return RccErrorConfig.WrongClockSource;
+    }
+
+    if (source == .HSE and current_clock.hse == 0) {
+        return RccErrorConfig.SourceClockNotInitialized;
+    }
+
+    const inputClock = if (source == .HSE) current_clock.hse else (current_clock.hsi >> 1);
+
+    const inputDiv = @intFromEnum(div) + 1;
+    const outputMul = @intFromEnum(mul) + 2;
+
+    const expectedPllOut = @divTrunc(inputClock, inputDiv) * outputMul;
+    if (expectedPllOut > 72_000_000) {
+        return RccErrorConfig.OutputPllTooHigh;
+    }
+
+    RCC.CFGR.modify(.{ .PLLSRC = comptime if (source == .HSE) .HSE_Div_PREDIV else .HSI_Div2, .PLLMUL = mul });
+    RCC.CR.modify(.{ .PLLON = 1 });
+
+    while (RCC.CR.read().PLLRDY != 1) {
+        asm volatile ("" ::: .{ .memory = true });
+    }
+
+    current_clock.pllout = expectedPllOut;
+}
+
+pub fn enable_hse(speed: u32) void {
+    RCC.CR.modify(.{ .HSEON = 1, .HSEBYP = 1 });
+
+    while (RCC.CR.read().HSERDY != 1) {
+        asm volatile ("" ::: .{ .memory = true });
+    }
+    current_clock.hse = speed;
+}
+
+pub fn select_pll_for_sysclk() RccErrorConfig!void {
+    if (current_clock.pllout == 0) {
+        return RccErrorConfig.PllMustBeEnableFirst;
+    }
+    // Maximum APB low speed domain is 36Nhz, let's divide by 2
+    if (current_clock.pllout > 36_000_000) {
+        RCC.CFGR.modify(.{ .PPRE1 = .Div2 });
+        current_clock.p1_clk = current_clock.pllout >> 1;
+    } else {
+        current_clock.p1_clk = current_clock.pllout;
+    }
+    RCC.CFGR.modify(.{ .SW = .PLL1_P });
+    current_clock.sys_clk = current_clock.pllout;
+    current_clock.h_clk = current_clock.pllout;
+    current_clock.p2_clk = current_clock.pllout;
+    current_clock.usart1_clk = current_clock.pllout;
+    adjust_flash();
+}
+
+fn adjust_flash() void {
+    if (current_clock.sys_clk < 24_000_000) {
+        FLASH.ACR.modify(.{ .LATENCY = .WS0 });
+    } else if (current_clock.sys_clk < 42_000_000) {
+        FLASH.ACR.modify(.{ .LATENCY = .WS1, .PRFTBE = 1 });
+    } else {
+        FLASH.ACR.modify(.{ .LATENCY = .WS2, .PRFTBE = 1 });
+    }
+}

port/stmicro/stm32/src/hals/STM32F303/uart.zig

@@ -97,13 +97,10 @@ pub fn Uart(comptime index: UartNum) type {
 
             // set the baud rate
             // TODO: Do not use the _board_'s frequency, but the _U(S)ARTx_ frequency
-            // from the chip, which can be affected by how the board configures the chip.
-            // In our case, these are accidentally the same at chip reset,
-            // if the board doesn't configure e.g. an HSE external crystal.
+            // from the chip
             // TODO: Do some checks to see if the baud rate is too high (or perhaps too low)
-            // TODO: Do a rounding div, instead of a truncating div?
-            const usartdiv = @as(u16, @intCast(@divTrunc(if (index == .UART1) rcc.current_clock.apb2 else rcc.current_clock.apb1, 9600)));
-            regs.BRR.raw = usartdiv;
+            const usartdiv = @divTrunc(if (index == .UART1) rcc.current_clock.usart1_clk else rcc.current_clock.p1_clk, config.baud_rate);
+            regs.BRR.raw = @as(u16, @intCast(usartdiv));
             // TODO: We assume the default OVER8=0 configuration above.
 
             // enable USART1, and its transmitter and receiver