aiger2: add crash test

Author: widlarizer

tests/techmap/abc_speed_gia_only.script

@@ -0,0 +1,28 @@
+&st
+&dch -r
+&nf
+&st
+&syn2
+&if -g -K 6
+&synch2 -r
+&nf
+&st
+&syn2
+&if -g -K 6
+&synch2 -r
+&nf
+&st
+&syn2
+&if -g -K 6
+&synch2 -r
+&nf
+&st
+&syn2
+&if -g -K 6
+&synch2 -r
+&nf
+&st
+&syn2
+&if -g -K 6
+&synch2 -r
+&nf

tests/techmap/xaiger2-5169.ys

@@ -0,0 +1,60 @@
+read_rtlil <<EOF
+
+# Generated by Yosys 0.53+98 (git sha1 780b12271, g++ 15.1.1 -fPIC -O3)
+autoidx 30
+attribute \top 1
+attribute \src "top.v:1.1-21.10"
+module \top
+  attribute \src "top.v:7.15-7.18"
+  wire output 1 \led
+  attribute \src "top.v:9.8-9.9"
+  wire \w
+  attribute \src "top.v:20.16-20.18"
+  cell $not $not$top.v:20$1
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \w
+    connect \Y \led
+  end
+  attribute \module_not_derived 1
+  attribute \src "top.v:10.10-18.4"
+  cell \CC_MX4 \mux
+    connect \D0 1'x
+    connect \D1 1'x
+    connect \D2 1'x
+    connect \D3 { }
+    connect \S0 1'x
+    connect \S1 1'x
+    connect \Y \w
+  end
+end
+
+EOF
+
+read_verilog -lib -specify <<EOF
+
+(* abc9_box, lib_whitebox *)
+module CC_MX4 (
+        input  D0, D1, D2, D3,
+        input  S0, S1,
+        output Y
+);
+        specify
+                (D0 => Y) = 453;
+                (D1 => Y) = 449;
+                (D2 => Y) = 488;
+                (D3 => Y) = 484;
+                (S0 => Y) = 422;
+                (S1 => Y) = 385;
+        endspecify
+
+        assign Y = S1 ? (S0 ? D3 : D2) :
+                        (S0 ? D1 : D0);
+
+endmodule
+
+EOF
+
+logger -expect error "Malformed design" 1
+abc_new -script abc_speed_gia_only.script -liberty ../../tests/liberty/normal.lib -liberty ../../tests/liberty/dff.lib