Skip to content
This repository was archived by the owner on Dec 22, 2021. It is now read-only.
Merged
Show file tree
Hide file tree
Changes from 1 commit
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
1 change: 1 addition & 0 deletions proposals/simd/BinarySIMD.md
Original file line number Diff line number Diff line change
Expand Up @@ -249,3 +249,4 @@ For example, `ImmLaneIdx16` is a byte with values in the range 0-15 (inclusive).
| `v128.store16_lane` | `TBD`| m:memarg, i:ImmLaneIdx8 |
| `v128.store32_lane` | `TBD`| m:memarg, i:ImmLaneIdx4 |
| `v128.store64_lane` | `TBD`| m:memarg, i:ImmLaneIdx2 |
| `i64x2.ne` | `TBD`| - |
1 change: 1 addition & 0 deletions proposals/simd/ImplementationStatus.md
Original file line number Diff line number Diff line change
Expand Up @@ -217,6 +217,7 @@
| `v128.store16_lane` | | | | | |
| `v128.store32_lane` | | | | | |
| `v128.store64_lane` | | | | | |
| `i64x2.ne` | | | | | |

[1] Tip of tree LLVM as of May 20, 2020

Expand Down
1 change: 1 addition & 0 deletions proposals/simd/SIMD.md
Original file line number Diff line number Diff line change
Expand Up @@ -735,6 +735,7 @@ def S.eq(a, b):
* `i8x16.ne(a: v128, b: v128) -> v128`
* `i16x8.ne(a: v128, b: v128) -> v128`
* `i32x4.ne(a: v128, b: v128) -> v128`
* `i64x2.ne(a: v128, b: v128) -> v128`
* `f32x4.ne(a: v128, b: v128) -> v128`
* `f64x2.ne(a: v128, b: v128) -> v128`

Expand Down