[AMDGPU] Serialize disjoint MFMA chains to hide DS_READ latency #728
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This patch identifies disjoint chains of dependent MFMA instructions (with length >= 2) and stitches them together into a single execution sequence by adding artificial dependencies from the tail of one chain to the head of the next. Currently, the scheduler may schedule disjoint MFMA chains too early or interleave them, which can expose high latencies from their associated DS_READ operands. By strictly serializing these MFMA chains, we force subsequent chains to execute later. This artificial delay increases the distance between the DS_READ issuance and the consuming MFMA instruction, effectively hiding the load latency.
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This patch identifies disjoint chains of dependent MFMA instructions (with length >= 2) and stitches them together into a single execution sequence by adding artificial dependencies from the tail of one chain to the head of the next.
Currently, the scheduler may schedule disjoint MFMA chains too early or interleave them, which can expose high latencies from their associated DS_READ operands. By strictly serializing these MFMA chains, we force subsequent chains to execute later. This artificial delay increases the distance between the DS_READ issuance and the consuming MFMA instruction, effectively hiding the load latency.