Updated for unbalanced pipeline

Author: shtaxxx

sample/tests/lib_pipeline/average/led.py

@@ -8,7 +8,7 @@ def mkLed():
     clk = m.Input('CLK')
     rst = m.Input('RST')
     x = m.Input('x', 32)
-    y = m.OutputReg('y', 32, initval=0)
+    y = m.Output('y', 32)
 
     pipe = lib.Pipeline(m, 'pipe')
 

sample/tests/lib_pipeline/average/test_led.py

@@ -91,14 +91,16 @@
   input CLK,
   input RST,
   input [32-1:0] x,
-  output reg [32-1:0] y
+  output [32-1:0] y
 );
 
   reg [32-1:0] _pipe_data_0;
   reg [32-1:0] _pipe_data_1;
   reg [32-1:0] _pipe_data_2;
   reg [32-1:0] _pipe_data_3;
   reg [32-1:0] _pipe_data_4;
+  reg [32-1:0] _pipe_data_5;
+  assign y = _pipe_data_5;
 
   always @(posedge CLK) begin
     if(RST) begin
@@ -107,14 +109,14 @@
       _pipe_data_2 <= 0;
       _pipe_data_3 <= 0;
       _pipe_data_4 <= 0;
-      y <= 0;
+      _pipe_data_5 <= 0;
     end else begin
       _pipe_data_0 <= x;
       _pipe_data_1 <= _pipe_data_0;
       _pipe_data_2 <= (_pipe_data_0 + _pipe_data_1);
       _pipe_data_3 <= x;
       _pipe_data_4 <= (_pipe_data_2 + _pipe_data_3);
-      y <= _pipe_data_4;
+      _pipe_data_5 <= _pipe_data_4;
     end
   end
 

sample/tests/lib_pipeline/average_valid/led.py

@@ -9,8 +9,8 @@ def mkLed():
     rst = m.Input('RST')
     x = m.Input('x', 32)
     vx = m.Input('vx')
-    y = m.OutputReg('y', 32, initval=0)
-    vy = m.OutputReg('vy', initval=0)
+    y = m.Output('y', 32)
+    vy = m.Output('vy')
 
     pipe = lib.Pipeline(m, 'pipe')
 

sample/tests/lib_pipeline/average_valid/test_led.py

@@ -103,8 +103,8 @@
   input RST,
   input [32-1:0] x,
   input vx,
-  output reg [32-1:0] y,
-  output reg vy
+  output [32-1:0] y,
+  output vy
 );
 
   reg [32-1:0] _pipe_data_0;
@@ -125,6 +125,11 @@
   reg _pipe_valid_4;
   reg [32-1:0] _pipe_data_5;
   reg _pipe_valid_5;
+  reg [32-1:0] _pipe_data_6;
+  reg _pipe_valid_6;
+
+  assign y = _pipe_data_6;
+  assign vy = _pipe_valid_6;
 
   always @(posedge CLK) begin
     if(RST) begin
@@ -140,8 +145,8 @@
       _pipe_valid_4 <= 0;
       _pipe_data_5 <= 0;
       _pipe_valid_5 <= 0;
-      y <= 0;
-      vy <= 0;
+      _pipe_data_6 <= 0;
+      _pipe_valid_6 <= 0;
     end else begin
       if(vx) begin
         _pipe_data_0 <= x;
@@ -173,8 +178,10 @@
         _pipe_data_5 <= (_pipe_data_3 + _pipe_data_4);
       end 
       _pipe_valid_5 <= (_pipe_valid_3 && _pipe_valid_4);
-      y <= _pipe_data_5;
-      vy <= _pipe_valid_5;
+      if(_pipe_valid_5) begin
+        _pipe_data_6 <= _pipe_data_5;
+      end 
+      _pipe_valid_6 <= _pipe_valid_5;
     end
   end
 

sample/tests/lib_pipeline/average_validready/led.py

@@ -10,8 +10,8 @@ def mkLed():
     x = m.Input('x', 32)
     vx = m.Input('vx')
     rx = m.Output('rx')
-    y = m.OutputReg('y', 32, initval=0)
-    vy = m.OutputReg('vy', initval=0)
+    y = m.Output('y', 32)
+    vy = m.Output('vy')
     ry = m.Input('ry')
 
     pipe = lib.Pipeline(m, 'pipe')

sample/tests/lib_pipeline/average_validready/test_led.py

@@ -199,36 +199,42 @@
   input [32-1:0] x,
   input vx,
   output rx,
-  output reg [32-1:0] y,
-  output reg vy,
+  output [32-1:0] y,
+  output vy,
   input ry
 );
 
+  assign rx = ((_pipe_ready_0 || (!_pipe_valid_0)) && (_pipe_ready_3 || (!_pipe_valid_3)));
   reg [32-1:0] _pipe_data_0;
   reg _pipe_valid_0;
   wire _pipe_ready_0;
   wire _pipe_nvalid_0;
   assign _pipe_nvalid_0 = ((vx && _pipe_valid_0) && _pipe_ready_0);
-  assign rx = (_pipe_ready_0 && (_pipe_ready_3 || (!_pipe_valid_3)));
+  assign _pipe_ready_0 = ((_pipe_ready_1 || (!_pipe_valid_1)) && (_pipe_ready_2 || (!_pipe_valid_2)));
   reg [32-1:0] _pipe_data_1;
   reg _pipe_valid_1;
   wire _pipe_ready_1;
   wire _pipe_nvalid_1;
   assign _pipe_nvalid_1 = ((vx && _pipe_valid_1) && _pipe_ready_1);
-  assign _pipe_ready_0 = (_pipe_ready_1 && (_pipe_ready_2 || (!_pipe_valid_2)));
+  assign _pipe_ready_1 = (_pipe_ready_2 || (!_pipe_valid_2));
   reg [32-1:0] _pipe_data_2;
   reg _pipe_valid_2;
   wire _pipe_ready_2;
-  assign _pipe_ready_1 = (_pipe_ready_2 || (!_pipe_valid_2));
+  assign _pipe_ready_2 = (_pipe_ready_4 || (!_pipe_valid_4));
   reg [32-1:0] _pipe_data_3;
   reg _pipe_valid_3;
   wire _pipe_ready_3;
+  assign _pipe_ready_3 = (_pipe_ready_4 || (!_pipe_valid_4));
   reg [32-1:0] _pipe_data_4;
   reg _pipe_valid_4;
   wire _pipe_ready_4;
-  assign _pipe_ready_2 = (_pipe_ready_4 || (!_pipe_valid_4));
-  assign _pipe_ready_3 = (_pipe_ready_4 || (!_pipe_valid_4));
-  assign _pipe_ready_4 = ry;
+  assign _pipe_ready_4 = (_pipe_ready_5 || (!_pipe_valid_5));
+  reg [32-1:0] _pipe_data_5;
+  reg _pipe_valid_5;
+  wire _pipe_ready_5;
+  assign _pipe_ready_5 = ry;
+  assign y = _pipe_data_5;
+  assign vy = _pipe_valid_5;
 
   always @(posedge CLK) begin
     if(RST) begin
@@ -242,8 +248,8 @@
       _pipe_valid_3 <= 0;
       _pipe_data_4 <= 0;
       _pipe_valid_4 <= 0;
-      y <= 0;
-      vy <= 0;
+      _pipe_data_5 <= 0;
+      _pipe_valid_5 <= 0;
     end else begin
       if((vx && (_pipe_ready_0 || (!_pipe_valid_0)))) begin
         _pipe_data_0 <= x;
@@ -275,8 +281,12 @@
       if((_pipe_ready_4 || (!_pipe_valid_4))) begin
         _pipe_valid_4 <= ((_pipe_valid_2 && _pipe_ready_2) && _pipe_valid_3);
       end 
-      y <= _pipe_data_4;
-      vy <= _pipe_valid_4;
+      if(((_pipe_valid_4 && _pipe_ready_4) && (_pipe_ready_5 || (!_pipe_valid_5)))) begin
+        _pipe_data_5 <= _pipe_data_4;
+      end 
+      if((_pipe_ready_5 || (!_pipe_valid_5))) begin
+        _pipe_valid_5 <= (_pipe_valid_4 && _pipe_ready_4);
+      end 
     end
   end
 

sample/tests/lib_pipeline/multi_input/test_led.py

@@ -258,28 +258,41 @@
   input rz
 );
 
+  assign rx = (_pipe_ready_0 || (!_pipe_valid_0));
+  assign ry = (_pipe_ready_0 || (!_pipe_valid_0));
   reg [32-1:0] _pipe_data_0;
   reg _pipe_valid_0;
   wire _pipe_ready_0;
-  assign rx = (_pipe_ready_0 || (!_pipe_valid_0));
-  assign ry = (_pipe_ready_0 || (!_pipe_valid_0));
-  assign z = _pipe_data_0;
-  assign vz = _pipe_valid_0;
-  assign _pipe_ready_0 = rz;
+  assign _pipe_ready_0 = (_pipe_ready_1 || (!_pipe_valid_1));
+  reg [32-1:0] _pipe_data_1;
+  reg _pipe_valid_1;
+  wire _pipe_ready_1;
+  assign _pipe_ready_1 = rz;
+  assign z = _pipe_data_1;
+  assign vz = _pipe_valid_1;
 
   always @(posedge CLK) begin
     if(RST) begin
       _pipe_data_0 <= 0;
       _pipe_valid_0 <= 0;
+      _pipe_data_1 <= 0;
+      _pipe_valid_1 <= 0;
     end else begin
       if((((vx && rx) && (vy && ry)) && (_pipe_ready_0 || (!_pipe_valid_0)))) begin
         _pipe_data_0 <= (x + y);
       end 
       if((_pipe_ready_0 || (!_pipe_valid_0))) begin
         _pipe_valid_0 <= ((vx && rx) && (vy && ry));
       end 
+      if(((_pipe_valid_0 && _pipe_ready_0) && (_pipe_ready_1 || (!_pipe_valid_1)))) begin
+        _pipe_data_1 <= _pipe_data_0;
+      end 
+      if((_pipe_ready_1 || (!_pipe_valid_1))) begin
+        _pipe_valid_1 <= (_pipe_valid_0 && _pipe_ready_0);
+      end 
     end
   end
+
 endmodule
 """
 

sample/tests/lib_pipeline/multi_output/test_led.py

@@ -406,27 +406,39 @@
   input ra
 );
 
+  assign rx = ((_pipe_ready_0 || (!_pipe_valid_0)) && (_pipe_ready_1 || (!_pipe_valid_1)));
+  assign ry = ((_pipe_ready_0 || (!_pipe_valid_0)) && (_pipe_ready_1 || (!_pipe_valid_1)));
   reg [32-1:0] _pipe_data_0;
   reg _pipe_valid_0;
   wire _pipe_ready_0;
-  assign rx = ((_pipe_ready_0 || (!_pipe_valid_0)) && (_pipe_ready_1 || (!_pipe_valid_1)));
-  assign ry = ((_pipe_ready_0 || (!_pipe_valid_0)) && (_pipe_ready_1 || (!_pipe_valid_1)));
+  assign _pipe_ready_0 = (_pipe_ready_2 || (!_pipe_valid_2));
   reg [32-1:0] _pipe_data_1;
   reg _pipe_valid_1;
   wire _pipe_ready_1;
-  assign z = _pipe_data_0;
-  assign vz = _pipe_valid_0;
-  assign _pipe_ready_0 = rz;
-  assign a = _pipe_data_1;
-  assign va = _pipe_valid_1;
-  assign _pipe_ready_1 = ra;
+  assign _pipe_ready_1 = (_pipe_ready_3 || (!_pipe_valid_3));
+  reg [32-1:0] _pipe_data_2;
+  reg _pipe_valid_2;
+  wire _pipe_ready_2;
+  assign _pipe_ready_2 = rz;
+  assign z = _pipe_data_2;
+  assign vz = _pipe_valid_2;
+  reg [32-1:0] _pipe_data_3;
+  reg _pipe_valid_3;
+  wire _pipe_ready_3;
+  assign _pipe_ready_3 = ra;
+  assign a = _pipe_data_3;
+  assign va = _pipe_valid_3;
 
   always @(posedge CLK) begin
     if(RST) begin
       _pipe_data_0 <= 0;
       _pipe_valid_0 <= 0;
       _pipe_data_1 <= 0;
       _pipe_valid_1 <= 0;
+      _pipe_data_2 <= 0;
+      _pipe_valid_2 <= 0;
+      _pipe_data_3 <= 0;
+      _pipe_valid_3 <= 0;
     end else begin
       if((((vx && rx) && (vy && ry)) && (_pipe_ready_0 || (!_pipe_valid_0)))) begin
         _pipe_data_0 <= (x + y);
@@ -440,6 +452,18 @@
       if((_pipe_ready_1 || (!_pipe_valid_1))) begin
         _pipe_valid_1 <= ((vy && ry) && (vx && rx));
       end 
+      if(((_pipe_valid_0 && _pipe_ready_0) && (_pipe_ready_2 || (!_pipe_valid_2)))) begin
+        _pipe_data_2 <= _pipe_data_0;
+      end 
+      if((_pipe_ready_2 || (!_pipe_valid_2))) begin
+        _pipe_valid_2 <= (_pipe_valid_0 && _pipe_ready_0);
+      end 
+      if(((_pipe_valid_1 && _pipe_ready_1) && (_pipe_ready_3 || (!_pipe_valid_3)))) begin
+        _pipe_data_3 <= _pipe_data_1;
+      end 
+      if((_pipe_ready_3 || (!_pipe_valid_3))) begin
+        _pipe_valid_3 <= (_pipe_valid_1 && _pipe_ready_1);
+      end 
     end
   end
 

sample/tests/lib_pipeline/passthrough/Makefile

@@ -0,0 +1,39 @@
+TARGET=led.py
+TEST=test_led.py
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv $(TEST)
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py *.out tmp.v uut.vcd
+
+.PHONY: sim
+sim:
+	iverilog -Wall tmp.v
+	./a.out
+
+.PHONY: view
+view:
+	gtkwave --giga uut.vcd &