make_reset in lib.FSM is updated for type check.

Author: shtaxxx

sample/tests/lib_pipeline/average/led.py

@@ -40,7 +40,10 @@ def mkTest(numports=8):
                      params=m.connect_params(led),
                      ports=m.connect_ports(led))
 
+    reset_done = m.Reg('reset_done', initval=0)
+    
     reset_stmt = []
+    reset_stmt.append( reset_done(0) )
     reset_stmt.append( x(0) )
 
     lib.simulation.setup_waveform(m, uut)
@@ -51,14 +54,31 @@ def mkTest(numports=8):
 
     init.add(
         Delay(1000),
+        reset_done(1),
         nclk(clk),
-        
-        [ ( x(i), nclk(clk) ) for i in range(10) ],
-        [ nclk(clk) for _ in range(10) ],
-        
+        Delay(10000),
         Systask('finish'),
     )
 
+    x_count = m.TmpReg(32, initval=0)
+
+    xfsm = lib.FSM(m, 'xfsm')
+    xfsm.goto_next(cond=reset_done)
+    xfsm.add(x.inc())
+    xfsm.add(x_count.inc())
+    xfsm.goto_next(cond=x_count==10)
+    xfsm.add( Systask('finish') )
+    
+    xfsm.make_always(clk, rst)
+    
+    
+    m.Always(Posedge(clk))(
+        If(reset_done)(
+            Systask('display', 'x=%d', x),
+            Systask('display', 'y=%d', y)
+        )
+    )
+    
     return m
 
 if __name__ == '__main__':

sample/tests/lib_pipeline/average/test_led.py

@@ -16,6 +16,8 @@
     .y(y)
   );
 
+  reg reset_done;
+
   initial begin
     $dumpfile("uut.vcd");
     $dumpvars(0, uut);
@@ -30,66 +32,58 @@
 
   initial begin
     RST = 0;
+    reset_done = 0;
     x = 0;
     #100;
     RST = 1;
     #100;
     RST = 0;
     #1000;
+    reset_done = 1;
     @(posedge CLK);
     #1;
-    x = 0;
-    @(posedge CLK);
-    #1;
-    x = 1;
-    @(posedge CLK);
-    #1;
-    x = 2;
-    @(posedge CLK);
-    #1;
-    x = 3;
-    @(posedge CLK);
-    #1;
-    x = 4;
-    @(posedge CLK);
-    #1;
-    x = 5;
-    @(posedge CLK);
-    #1;
-    x = 6;
-    @(posedge CLK);
-    #1;
-    x = 7;
-    @(posedge CLK);
-    #1;
-    x = 8;
-    @(posedge CLK);
-    #1;
-    x = 9;
-    @(posedge CLK);
-    #1;
-    @(posedge CLK);
-    #1;
-    @(posedge CLK);
-    #1;
-    @(posedge CLK);
-    #1;
-    @(posedge CLK);
-    #1;
-    @(posedge CLK);
-    #1;
-    @(posedge CLK);
-    #1;
-    @(posedge CLK);
-    #1;
-    @(posedge CLK);
-    #1;
-    @(posedge CLK);
-    #1;
-    @(posedge CLK);
-    #1;
+    #10000;
     $finish;
   end
+
+  reg [32-1:0] _tmp_0;
+  reg [32-1:0] xfsm;
+  localparam xfsm_init = 0;
+  localparam xfsm_1 = 1;
+  localparam xfsm_2 = 2;
+
+  always @(posedge CLK) begin
+    if(RST) begin
+      xfsm <= xfsm_init;
+      _tmp_0 <= 0;
+    end else begin
+      case(xfsm)
+        xfsm_init: begin
+          if(reset_done) begin
+            xfsm <= xfsm_1;
+          end 
+        end
+        xfsm_1: begin
+          x <= x + 1;
+          _tmp_0 <= _tmp_0 + 1;
+          if(_tmp_0 == 10) begin
+            xfsm <= xfsm_2;
+          end 
+        end
+        xfsm_2: begin
+          $finish;
+        end
+      endcase
+    end
+  end
+
+  always @(posedge CLK) begin
+    if(reset_done) begin
+      $display("x=%d", x);
+      $display("y=%d", y);
+    end 
+  end
+
 endmodule
 
 module blinkled
@@ -117,12 +111,13 @@
     end else begin
       _pipe_data_0 <= x;
       _pipe_data_1 <= _pipe_data_0;
-      _pipe_data_2 <= _pipe_data_0 + _pipe_data_1;
+      _pipe_data_2 <= (_pipe_data_0 + _pipe_data_1);
       _pipe_data_3 <= x;
-      _pipe_data_4 <= _pipe_data_2 + _pipe_data_3;
+      _pipe_data_4 <= (_pipe_data_2 + _pipe_data_3);
       y <= _pipe_data_4;
     end
   end
+
 endmodule
 """
 

sample/tests/lib_pipeline/average_valid/led.py

@@ -44,7 +44,10 @@ def mkTest(numports=8):
                      params=m.connect_params(led),
                      ports=m.connect_ports(led))
 
+    reset_done = m.Reg('reset_done', initval=0)
+    
     reset_stmt = []
+    reset_stmt.append( reset_done(0) )
     reset_stmt.append( x(0) )
     reset_stmt.append( vx(0) )
 
@@ -56,15 +59,37 @@ def mkTest(numports=8):
 
     init.add(
         Delay(1000),
+        reset_done(1),
         nclk(clk),
-        
-        [ ( x(i), vx(1), nclk(clk), [ (vx(0), nclk(clk)) for _ in range(3)] ) for i in range(10) ],
-        vx(0),
-        [ nclk(clk) for _ in range(10) ],
-        
+        Delay(10000),
         Systask('finish'),
     )
 
+
+    x_count = m.TmpReg(32, initval=0)
+    
+    xfsm = lib.FSM(m, 'xfsm')
+    xfsm.add(vx(0))
+    xfsm.goto_next(cond=reset_done)
+    xfsm.add(vx(1))
+    xfsm.add(x.inc())
+    xfsm.add(x_count.inc())
+    xfsm.goto_next(cond=x_count==10)
+    xfsm.add(vx(0))
+    xfsm.make_always(clk, rst)
+
+    
+    m.Always(Posedge(clk))(
+        If(reset_done)(
+            If(vx)(
+                Systask('display', 'x=%d', x)
+            ),
+            If(vy)(
+                Systask('display', 'y=%d', y)
+            )
+        )
+    )
+    
     return m
 
 if __name__ == '__main__':