Rename

shtaxxx · shtaxxx · commit e1509dd76939 · 2022-03-18T14:33:10.000+09:00
diff --git a/veriloggen/types/axi.py b/veriloggen/types/axi.py
@@ -3667,7 +3667,7 @@ def write_word(self, fsm, word_index, byte_offset, wdata, bits=8):
         return 0
 
 
-class AxiSerialMultiportMemoryModel(AxiMemoryModelOld):
+class AxiSerialMultiportMemoryModel(AxiSerialMemoryModel):
     __intrinsics__ = ('read', 'write',
                       'read_word', 'write_word')
 
