Rename

Author: shtaxxx

veriloggen/types/axi.py

@@ -3288,7 +3288,7 @@ def connect(self, index, ports, name):
         self.rdatas[index].rready.connect(rready)
 
 
-class AxiMemoryModelOld(AxiSlave):
+class AxiSerialMemoryModel(AxiSlave):
     __intrinsics__ = ('read', 'write',
                       'read_word', 'write_word')
 
@@ -3667,7 +3667,7 @@ def write_word(self, fsm, word_index, byte_offset, wdata, bits=8):
         return 0
 
 
-class AxiMultiportMemoryModelOld(AxiMemoryModelOld):
+class AxiSerialMultiportMemoryModel(AxiMemoryModelOld):
     __intrinsics__ = ('read', 'write',
                       'read_word', 'write_word')