OutputReg in interface

Author: shtaxxx

veriloggen/interface.py

@@ -22,6 +22,10 @@ def Output(self, name, width=1, length=None, signed=False, value=None):
         new_name = self.prefix + name + self.postfix
         return self.module.Output(name, width, length, signed, value)
 
+    def OutputReg(self, name, width=1, length=None, signed=False, value=None):
+        new_name = self.prefix + name + self.postfix
+        return self.module.OutputReg(name, width, length, signed, value)
+        
     def Inout(self, name, width=1, length=None, signed=False, value=None):
         new_name = self.prefix + name + self.postfix
         return self.module.Inout(name, width, length, signed, value)

veriloggen/toverilog.py

@@ -12,7 +12,6 @@
 #-------------------------------------------------------------------------------
 def toVerilog(node):
     visitor = VerilogModuleVisitor()
-    #verilogdef = visitor.visit(node)
     verilogdef = visitor.visit(node)
     codegen = ASTCodeGenerator()
     return codegen.visit(verilogdef)