Dockerfile is added. Interface and its example is updated.

Author: shtaxxx

MANIFEST.in

@@ -1,2 +1,4 @@
 include README.md
 include README.rst
+include docker/Dockerfile
+

Makefile

@@ -5,7 +5,7 @@ all: clean
 clean:
 	make clean -C ./veriloggen
 	make clean -C ./sample
-	rm -rf *.pyc __pycache__ pycoram.egg-info build dist
+	rm -rf *.pyc __pycache__ veriloggen.egg-info build dist
 
 .PHONY: release
 release:

README.md

@@ -39,6 +39,22 @@ Requirements
 Installation
 ==============================
 
+On Docker
+------------------------------
+
+Dockerfile is available, so that you can try Veriloggen on Docker without any installation on your host platform.
+
+```
+cd docker
+sudo docker build -t user/veriloggen .
+sudo docker run --name veriloggen -i -t user/veriloggen /bin/bash
+cd veriloggen/sample/led/
+make
+```
+
+On your host platform
+------------------------------
+
 If you want to use Veriloggen as a general library, you can install on your environment by using setup.py.
 
 If Python 2.7 is used,

README.rst

@@ -59,6 +59,17 @@ If Python 3.x is used,
 
     python3 setup.py install
 
+Docker
+------
+
+Dockerfile is available. Please try Veriloggen by using Dockerfile.
+
+::
+
+    cd docker
+    sudo docker build -t user/ubuntu:14.04-veriloggen .
+    sudo docker run --name veriloggen -i -t user/ubuntu:14.04-veriloggen /bin/bash
+
 Getting Started
 ===============
 

docker/Dockerfile

@@ -0,0 +1,17 @@
+FROM ubuntu:14.04
+RUN apt-get update && apt-get upgrade -y
+RUN apt-get install build-essential -y
+RUN apt-get install git -y
+RUN apt-get install python python-pip python3 python3-pip -y
+RUN apt-get install iverilog gtkwave -y
+RUN apt-get install python-pygraphviz -y
+RUN pip install jedi epc virtualenv jinja2
+RUN pip3 install jedi epc virtualenv jinja2
+RUN mkdir /home/veriloggen/
+WORKDIR "/home/veriloggen"
+RUN git clone https://github.com/shtaxxx/Pyverilog.git
+RUN cd Pyverilog && python setup.py install && cd ../
+RUN cd Pyverilog && python3 setup.py install && cd ../
+RUN git clone https://github.com/shtaxxx/veriloggen.git
+RUN cd veriloggen && python setup.py install && cd ../
+RUN cd veriloggen && python3 setup.py install && cd ../

sample/bram/bram.py

@@ -1,82 +1,82 @@
 import sys
 import os
+import collections
+
 from veriloggen import *
 
-def mkBramInterface(m, addrwidth, datawidth):
-    addr = m.Input('addr', addrwidth)
-    datain = m.Input('datain', datawidth)
-    write = m.Input('write')
-    dataout = m.Output('dataout', datawidth)
-    return addr, datain, write, dataout
-    
-def mkBramUser(m, name, addrwidth, datawidth):
-    addr = m.Reg(name + 'addr', addrwidth)
-    datain = m.Reg(name + 'datain', datawidth)
-    write = m.Reg(name + 'write')
-    dataout = m.Wire(name + 'dataout', datawidth)
-    return addr, datain, write, dataout
+class BramInterface(Interface):
+    def __init__(self, m, prefix, postfix, addrwidth, datawidth, io=False):
+        Interface.__init__(self, m, prefix, postfix, io)
+        
+        self.addrwidth = self.Parameter('ADDR_WIDTH', addrwidth)
+        self.datawidth = self.Parameter('DATA_WIDTH', datawidth)
+        
+        In = self.Input if self.io else self.Reg # self.Wire
+        Out = self.Output if self.io else self.Wire 
+        
+        self.addr = In('addr', addrwidth)
+        self.datain = In('datain', datawidth)
+        self.write = In('write')
+        self.dataout = Out('dataout', datawidth)
 
 def mkBram(name):
-    m = Module(name + '_bram')
+    m = Module(name + 'bram')
+    
     addrwidth = m.Parameter('ADDR_WIDTH', 10)
     datawidth = m.Parameter('DATA_WIDTH', 32)
+    
     clk = m.Input('CLK')
-    addr, datain, write, dataout = mkBramInterface(m, addrwidth, datawidth)
-    d_addr = m.Reg('d_' + addr.name, datawidth)
-    mem = m.Reg('mem', datawidth, addrwidth)
+    bramif = BramInterface(m, '', '', addrwidth, datawidth, io=True)
+    
+    d_addr = m.Reg('d_' + bramif.addr.name, datawidth)
+    mem = m.Reg('mem', datawidth, Int(2)**addrwidth)
 
     m.Always(Posedge(clk))(
-        If(write)( mem[addr](datain) ),
-        d_addr(addr)
+        If(bramif.write)( mem[bramif.addr](bramif.datain) ),
+        d_addr(bramif.addr)
     )
-    m.Assign(dataout(mem[d_addr]))
-
+    
+    m.Assign(bramif.dataout(mem[d_addr]))
+    
     return m
 
-def mkUser(bram):
+def mkTop():
     m = Module('TOP')
     addrwidth = m.Parameter('ADDR_WIDTH', 10)
     datawidth = m.Parameter('DATA_WIDTH', 32)
     clk = m.Input('CLK')
     rst = m.Input('RST')
-    addr, datain, write, dataout = mkBramUser(m, 'my_', addrwidth, datawidth)
+    bramif = BramInterface(m, 'bram_', '', addrwidth, datawidth)
+
+    params = collections.OrderedDict()
+    params.update(bramif.connectAllParameters())
 
-    params = ('ADDR_WIDTH', addrwidth), ('DATA_WIDTH', datawidth)
-    ports = ('CLK', clk), ('addr', addr), ('datain', datain), ('write', write), ('dataout', dataout)
+    ports = collections.OrderedDict()
+    ports.update(clk.connect())
+    ports.update(bramif.connectAllPorts())
+
     m.Instance(bram, 'inst_bram', params, ports)
 
-    state = m.Reg('state', 32)
-    
-    label = []
-    label.append(m.Localparam('INIT' + str(len(label)), len(label)))
-    
-    def cond(name='label'):
-        ret = state == label[-1]
-        label.append(m.Localparam(name + str(len(label)), len(label)))
-        return ret
-    
-    def goto_next():
-        return state( state + 1 )
-    
+    fsm = lib.FSM(m, 'fsm')
     m.Always(Posedge(clk))(
         If(rst)(
-            addr(0), datain(0), write(0), state(0)
+            bramif.addr(0), bramif.datain(0), bramif.write(0), fsm.next(0)
         ).els(
-            If(cond())( addr(0), datain(0), write(0), goto_next() ),
-            If(cond())( write(1), datain(datain + 4), goto_next() ),
-            If(cond())( write(0), goto_next() ),
-            If(cond())(
-                If(addr == 128)(
-                    addr(0), state(label[0])
+            fsm( bramif.addr(0), bramif.datain(0), bramif.write(0), fsm.next() ),
+            fsm( bramif.datain(bramif.datain + 4), fsm.next() ),
+            fsm( bramif.write(0), fsm.next() ),
+            fsm( 
+                If(bramif.addr == 128)(
+                    bramif.addr(0), fsm.next(0)
                 ).els(
-                    addr(addr + 1), state(label[1])
-                )
-            )))
+                    bramif.addr(bramif.addr + 1), fsm.next(1)
+                ))
+            ))
 
     return m
 
 #-------------------------------------------------------------------------------
-bram = mkBram('my')
-user = mkUser(bram)
-verilog = ''.join( (bram.toVerilog(), user.toVerilog()) )
+bram = mkBram('my_')
+top = mkTop()
+verilog = ''.join( (bram.toVerilog(), top.toVerilog()) )
 print(verilog)

sample/led-module/Makefile

@@ -0,0 +1,25 @@
+TARGET=led.py
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: run
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py *.out

sample/led-module/led.py

@@ -0,0 +1,79 @@
+import sys
+import os
+from veriloggen import *
+
+class Led(Module):
+    def __init__(self, name='blinkled'):
+        Module.__init__(self, name)
+        self.width = self.Parameter('WIDTH', 8)
+        self.clk = self.Input('CLK')
+        self.rst = self.Input('RST')
+        self.led = self.OutputReg('LED', self.width)
+        self.count = self.Reg('count', 32)
+
+        self.Always(Posedge(self.clk))(
+            If(self.rst)(
+                self.count(0)
+            ).els(
+                self.count(self.count + 1)
+            ))
+        
+        self.Always(Posedge(self.clk))(
+            If(self.rst)(
+                self.led(0)
+            ).els(
+                If(self.count == 1024 - 1)(
+                    self.led(self.led + 1)
+                )
+            ))
+        
+#-------------------------------------------------------------------------------
+led = Led()
+verilog = led.toVerilog()
+print(verilog)
+
+#-------------------------------------------------------------------------------
+expected_verilog = """
+module blinkled #
+  ( 
+   parameter WIDTH = 8
+  )
+  ( 
+   input CLK, 
+   input RST,
+   output reg [WIDTH-1:0] LED
+  );
+  reg [32-1:0] count;
+
+  always @(posedge CLK) begin
+    if(RST) begin
+      count <= 0;
+    end else begin
+      count <= count + 1;
+    end
+  end
+  always @(posedge CLK) begin
+    if(RST) begin
+      LED <= 0;
+    end else begin
+      if(count == 1023) begin
+        LED <= LED + 1;
+      end 
+    end
+  end
+endmodule
+"""
+
+#from pyverilog.vparser.parser import VerilogParser
+#from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+#parser = VerilogParser()
+#expected_verilog_ast = parser.parse(expected_verilog)
+#codegen = ASTCodeGenerator()
+#expected_verilog_code = codegen.visit(expected_verilog_ast)
+
+#print('// Sample Verilog code -> AST -> Verilog code')
+#print(expected_verilog_code)
+
+#import difflib
+#diff = difflib.unified_diff(verilog.splitlines(), expected_verilog_code.splitlines())
+#print('\n'.join(list(diff)))

sample/led-module/veriloggen

@@ -0,0 +1 @@
+../../veriloggen