unused wires removed

Author: shtaxxx

examples/thread_verilog_submodule_ipcore/test_thread_verilog_submodule_ipcore.py

@@ -1089,9 +1089,6 @@
   reg start;
   wire busy;
   reg [ADDR_WIDTH-1:0] size;
-  wire pe_start;
-  wire pe_busy;
-  wire [ADDR_WIDTH-1+1-1:0] pe_size;
   wire [ADDR_WIDTH-1+1-1:0] pe_addr;
   wire [DATA_WIDTH-1+1-1:0] pe_rdata;
   wire [DATA_WIDTH-1+1-1:0] pe_wdata;

examples/thread_verilog_submodule_ipcore/thread_verilog_submodule_ipcore.py

@@ -124,8 +124,7 @@ def mkMemcpy():
                                 ('DATA_WIDTH', datawidth)),
                     arg_ports=(('CLK', clk), ('RST', rst),
                                ('start', start), ('busy', busy), ('size', size)),
-                    as_wire=('start', 'busy', 'size',
-                             'addr', 'rdata', 'wdata', 'wenable'))
+                    as_wire=('addr', 'rdata', 'wdata', 'wenable'))
 
     # connect ports to RAM
     ram_a.connect_rtl(1, sub['addr'], sub['wdata'],